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| 研究生： |
陳昱仁 Yu-Ren Chen |
|---|---|
| 論文名稱： |
具動態指令排程之RISC-V 128位元極長指令核心設計 Design of a RISC-V-based 128-bit VLIW Core with Dynamic Instruction Scheduling |
| 指導教授： |
林昌鴻
Chang-Hong Lin |
| 口試委員: |
林淵翔
Yuan-Hsiang Lin 沈中安 Chung-An Shen 劉一宇 Yi-Yu Liu |
| 學位類別： |
碩士 Master |
| 系所名稱： |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
| 論文出版年： | 2023 |
| 畢業學年度： | 111 |
| 語文別： | 英文 |
| 論文頁數： | 56 |
| 中文關鍵詞： | VLIW 、動態指令排程 、RISC-V |
| 外文關鍵詞： | VLIW, dynamic instruction scheduling, RISC-V |
| 相關次數： | 點閱：168 下載：2 |
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由於極長指令處理器經常遇到二進制程式不相容及軟體維護的問題，自編譯器支援、指令集架構至管線化硬體實作。本論文設計了一個支援RISC-V RV32I及RV32M指令集的128位元極長指令處理器。為了原生支援RISC-V編譯器工具組，我們基於經典的RISC五階段管線化設計，整合了數個運用於超純量處理器的設計技巧，例如引入額外的排程階段以分析各指令間的相依性，並組合成無危障的指令封包。而後以Verilog硬體描述語言將此概念實現並合成至Kintex-7 XC7K160TFBG484-1 FPGA上，得到IPC為0.953、頻率為70.921 MHz之極長指令處理器。共硬體資源使用率上為16877（16.64%）個查找表及5866（2.89%）個暫存器切片。與單指令執行的核心為基準相比，此設計以0.865倍的頻率換得1.395倍的IPC。
The shortcomings of Very Long Instruction Word (VLIW) architectures include binary incompatibility and software maintenance problems, varying from compiler support, instruction set architectures (ISA) to physical implementations such as pipelining. To solve this, this thesis proposed a RISC-V-based 128-bit Very Long Instruction Word (VLIW) core design, which supports the RISC-V RV32I and the RV32M ISA. In order to natively support the RISC-V compiler toolchain, based on the classical 5-pipeline RISC design, we integrated several techniques used in a typical superscalar design. For example, we introduced an additional scheduler stage to analyze instruction dependencies and to dispatch them into hazard-free instruction packets. Later, the concept is designed with Verilog HDL and synthesized on a Kintex-7 XC7K160TFBG484-1 FPGA, yielding an IPC of 0.953, a frequency of 70.921 MHz, with 16877 (16.64%) LUTs and 5866 (2.89%) slice registers resource utilized. Compared to the single-issue core, it trades off 0.865 times the baseline in frequency with 1.395 times the baseline in IPC.
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