在現行的微處理器的設計中，由於各種手持裝置、平板電腦的流行，使得能源消耗逐漸成為一個至關重要的議題。製程上的進步，也直接的影響晶片中靜態電能的消耗比率，由此衍生出各式各樣針對減少靜態電能消耗的機制。其中，本篇論文著重於探討電源閘控這項技術。電源閘控又分為兩個種類，分別是使用硬體層面控制跟軟體層面控制兩種不同的策略來減低靜態電源的消耗。本文中，利用修改過的Binary Translator透過軟體的角度觀察出合適的機制，分析出硬體策略還是軟體策略的電源閘控能夠減少更多的靜態電能消耗。

為了在軟體的層面模擬硬體電源閘控的行為，需要一個透過Path-Guided Hardware-Based Power Gating Data Flow Analysis ，來增加分析以及預測的精準度。

Power reduction is an important design consideration of microprocessor. With shrinking technologies, the percentage of leakage power on chip also increases and becomes an innegligible problem. Therefore, reducing leakage power dissipation has become an important issue. According to our observation, hardware-based power gating (HWPG) can get a better power saving than software-based power gating (SWPG), but SWPG can perform bet ter than HWPG for some special applications. Hence, we propose a path-guided hardware-based power gating selection strategy to select power gating strategy. In our approach, HWPG is the default method and then SWPG will be applied for the case that the power saving .

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