微處理器是高效能伺服器系統中最大的功率消耗來源。卻受限於記憶體、硬碟及其他I/O裝置運作速度無法運作在高使用率的狀態下而造成電力浪費，降低微處理器的耗電問題已經成為伺服器系統設計重要議題之一。隨著資料處理量高速成長，為加快運算效率及提升處理量，多核心多處理器已經成為高效能伺服器主流之微處理器架構。探討微處理器電源管理技術之研究多以動態電壓與頻率調節(DVFS)和per-core power gating (PCPG)或動態電壓與頻率調節(DVFS)和CPU packing為主。
數位資料巨量成長，儲存伺服器的需求逐年增加。儲存伺服器需要執行大量的檔案存取，因為磁碟存取速度遠低於記憶體速度，使得微處理器經常處在低使用率情況。本論文運用DVFS、PCPG和CPU packing三種技術，實現在儲存應用於多核心多處理器之低功率系統。其目的在於減少所有微處理器及其核心同時開啟而等待硬碟存取動作所產生之耗電。實驗結果顯示，多核心多處理器系統在硬碟資料存取使用:合併DVFS及PCPG可減少16.85%的耗電，合併DVFS及CPU packing可減少52.98%的耗電。

Microprocessor is the largest power consumption source in a high efficient server system. Due to the slow executing speed of the memory, hard disks and other I/O devices, it can’t always be in high utilization and causes power waste, reducing power consumption of microprocessor has became one of the important topics in server system design. With the explosive growth of data processing capacity demand, multi-core multiprocessor is the mainstream microprocessor structure of the high efficient server for increasing the efficiency and capability of computing. Most researches of microprocessor power management focus on dynamic voltage and frequency technology (DVFS) and per-core power gating(PCPG) or dynamic voltage and frequency technology (DVFS) and CPU packing.

Due to the explosive growth of digital data, the storage server demands increase every year. It needs to execute large data access, but because the disk access speed is slower than the memory access speed, thus microprocessor usually execute in low utilization. In this thesis, it uses three technologies: DVFS, PCPG and CPU packing to execute a low power system of multicore multiprocessor in storage application. Its purpose is to reduce the power consumption that all processors and its cores are running at the same time, but they are idle to wait accessing to hard disc. The experiment shows that multicore multiprocessor can reduce 20.26% of power consumption when it uses DVFS and PCPG at the same time; it can reduce 52.98% of power consumption when it uses DVFS and CPU packing at the same time.

[1] P. Bai, “Advancing Moore's law: Challenges and opportunities”, Proceedings of the 8th IEEE International Conference on ASIC, 2009. pp 7-8.
[2] S. Krishnan, S.V. Garimella, G.M.Chrysler and R.V. Mahajan, “Towards a Thermal Moore’s Law”, Proceedings of IEEE Transactions on Advanced Packaging, Vol. 30, No. 3, 2007. pp 462–474.
[3] T. Mudge, “Power: a first class architectural design constraint”, Proceedings of IEEE Journal of Computer, Vol. 34, Issue 4, 2001. pp 52–58.
[4] M. Pedram, S. Nazarian, “Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods”, Proceedings of the IEEE Vol. 94, No. 8, 2006. pp 1487-1501.
[5] D. Niyato, S. Chaisiri, and B.S. Lee, “Optimal power management for server farm to support green computing”, Proceedings of the 9th IEEE/ACM International Symposium on Cluster Computing and the Grid, 2009. pp 84 – 91.
[6] P. Bohrer, N.E. Elmootazbellah , T. Keller, M. Kistler, C. Lefurgy, and R. Rajamony, “The Case for Power Management in Web Servers”, Power aware computing, Kluwer Academic Publishers, 2002.
[7] C-H. Hsu, U. Kremer, “The design implementation and evaluation of a compiler algorithm for CPU energy reduction”, Proceedings of ACM SIGPLAN Conference on programming Language Design and Implementation, 2003.
[8] R. Zamani, A.Afsahi, Y. Qian, C, Hamacher, ”A Feasibility Analysis of Power-Awareness and Energy Minimization in Modern Interconnects for High-Performance Computing”, Proceedings of the 2007 IEEE International Conference on Cluster Computing, 2007. pp 118 – 128.
[9] G. Hinton, Key Nehalem Choices, 2010. Http://www.stanford.edu/class/ee380/Abstracts/100217-slides.pdf
[10] Intel and Core i7 (Nehalem) Dynamic Power Management.
Http://cs466.andersonje.com/public/pm.pdf
[11] 黃慕凱，「多核心處理器之群組式動態電源管理機制」，碩士論文，國立台灣科技
大學，台北(2011)。
[12] S. Gochman, R. Ronen, I. Anati, A. Berkovits, T. Kurts, A. Naveh, A. Saeed, Z. Sperber, and R. C. Valentine,” The Intel Pentium M Processor: Micro-architecture and Performance”, Intel Technology Journal, Vol. 7, Issue 2, 2003.
[13] AMD PowerNow document. http://www.amd.com/
[14] Intel and Core i7 (Nehalem) Dynamic Power Management.
http://cs466.andersonje.com/public/pm.pdf
[15] J. Kong, J. Choi, L. Choi, S. Chung, “ Low-Cost Application-Aware DVFS for Multi-core Architecture“, Proceedings of the 3rd International Conference on Convergence and Hybrid Information Technology, 2008. pp 106 - 111.
[16] L. Miao, Y. Qi, D. Hou, C. Wu and Y. Dai, ”Dynamic Power Management and Dynamic Voltage Scaling in Real-time CMP Systems“, Proceedings of Networking, Architecture, and Storage (NAS) Conference, 2007. pp 249-250.
[17] K. Choi,R. Soma, and M. Pedram, “Dynamic Voltage and Frequency Scaling
based on Workload Decomposition“, Proceedings of the International Symposium on Low Power Electronics and Design,2004. pp 174-179.
[18] J. Leverich, M. Monchiero, V. Talwar, P. Ranganathan and C. Kozyrakis, “Power Management of Datacenter Workloads Using a Power Gating“, Proceedings of IEEE Computer Architecture Letters, 2009. pp 48-51.
[19] N. Madan, A. Buyuktosunoglu, P. Bose and M. Annavaram, “A case for
guarded power gating for multi-core processors“, Proceedings of IEEE 17th
International Symposium on High Performance Computer Architecture, pp
291-300.
[20] J.Lee, N. S Kim, “Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating“, Proceedings of the 46th Annual Design Automation Conference, 2009.pp 47-50.
[21] J. Lee, N. S Kim, “Analyzing Potential Throughput Improvement of Power and Thermal Constrained Multicore Processors by Exploiting DVFS and PCPG“,
Proceedings of Very Large Scale Integration (VLSI) Systems, IEEE Transactions, 2011. pp 1-11.
[22] S. Ghiasi and W. Felter, “CPU Packing for Multiprocessor Power Reduction“, Proceedings of Power - Aware Computer Systems (PACS) Conference, 2003 .pp
117-131
[23] V.W. Freeh, T.K.Bletsch and F.L. Rawson, “Scaling and Packing on a Chip
Multiprocessor“, Proceedings of the IEEE International Symposium on Parallel and Distributed Processing, 2007. pp 1-8.
[24] N. Kappiah, V. W. Freeh, and D. K. Lowenthal, “Just in time dynamic voltage scaling: Exploiting inter-node slack to save energy in MPI programs“, Proceedings of the ACM /IEEE SC Conference, 2005.pp 33
[25] S. Kavalanekar, B.Worthington, Q. Zhang, V.Sharda, “Characterization of storage workload traces from production Windows servers“, Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), 2008,pp 119–128
[26] ADVANCED CONFIGURATION AND POWER INTERFACE (ACPI) SPECIFICATION:
http://www.acpi.info/spec.htm
[27] Enhanced Intel SpeedStep Technology for the Intel Pentium M Processor White Paper, Intel Corporation, 2004. Http://download.intel.com/design/network/papers/30117401.pdf
[28] Intel Turbo Boost Technology in Intel Core Microarchitecture (Nehalem) Based Processors White Paper, 2008 .
http://download.intel.com/design/processor/applnots/320354.pdf
[29] Quad-Core Intel® Xeon® Processor 5400 Series Electrical, Mechanical, and Thermal Specification (EMTS) http://www.intel.com/assets/pdf/datasheet/318589.pdf