動態隨機存取記憶體(DRAM)為現今眾多電子產品中不可或缺的重要零組件。其中記憶元件的基本架構是由一個電晶體元件做為開關使用和一個電容元件做為儲存電荷功能所組成。本文是從製程整合的觀點來討論電容元件的圖形結構和製程設計。在近代DRAM製程的歷史中，由於電容元件結構設計上的差異，分為溝槽(Deep Trench)技術和堆疊(Stack)技術。兩個技術的不同處在於溝槽技術為先製作電容，然後再製作電晶體。電容元件在矽晶圓表平面之下而電晶體則是在矽晶圓表平面之上。堆疊技術是先製作電晶體元件之後才製作電容元件。其電容元件是堆疊在電晶體元件上。電晶體的製程技術依世代的不同，目前的主流為將閘極通道(Gate-Channel)製作在矽晶圓表平面下以節省元件所佔的平面面積(Buried Word-line)。溝槽技術隨著德商奇夢達(Qimonda)於2009年初申請破產保護後，70奈米DRAM 成了該技術的最後一個有進入到正式量產之世代。堆疊式記憶體技術成了近年來唯一、並持續進行微縮的製程。
文中涵蓋了堆疊式記憶體電容元件目前所使用的主要製程技術和多重圖形轉印技術並提出新的設計來增加電容值的同時也能提供良好的結構支撐。
除了提出新的製程技術來增加電容值，本文也提出了新的設計來克服多重圖形轉印技術的圖形均勻性調整問題。此新設計使得製程工程師在使用多重圖形轉印技術時由原本至少要花費19片晶圓才能得到圖曝光的中心值，簡化成用1片晶圓就能收到19片晶圓的實驗結果。大大的減少了調整電容圖形所需花費的資源和降低因為晶圓和晶圓間差異所導致的數據誤判。

Dynamic random access memory (DRAM) is a necessary and important component of various electronic products. The basic architecture of a DRAM device consists of a transistor element as a switch function device and a storage capacitor element as a charge storage device. This article discusses the structure and process design of the storage capacitor device in the DRAM field, from process integration point of view. In the history of contemporary DRAM process, due to structural design differences of storage capacitors, it is divided into two technologies: Deep-trench DRAM and Stack DRAM. The major difference between the two technologies is Deep-trench technology makes storage capacitor first then produces transistor later. Storage capacitor cells are sited below the plane of a silicon wafer and transistor is above a silicon wafer surface. On the other hand, in Stack DRAM technique, chip makers manufacture the storage capacitor after fabricating transistor device. So, Storage capacitor cells are stacked on transistor elements. Process technology of the transistor is different from generation to generation. Currently, the mainstream of DRAM transistor technology is to make the gate channel under the surface of a silicon wafer to save cell array area (Buried word-line). About Trench DRAM, after Qimonda filed for bankruptcy protection in early 2009, 70nm DRAM became the final massed production generation. Hence, Stack DRAM technology has become the only one DRAM technology.
This thesis analyses the main process of Stacked-Capacitor also cover multiple patterning transfer technologies currently using, and proposes a new design to increase the capacitance value. The design can increase the capacitance of the storage node and provides better structural supporting than other DRAM manufacturers. This thesis also presents a novel design to overcome the problem of multiple patterning transfer technologies uniformity adjustment. Usually, process designers need a lot of wafers resource to obtain the best CD uniformity when they use the multiple patterning transfer techniques such as SADP or SARP. This new design with multiple patterning scheme can collect 19 kinds of CD uniformity onto a single wafer. The resource requirements for CD uniformity adjusting are significantly reduced. Also, the design saves a lot of learning time.

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