在射頻通訊系統中，鎖相迴路(PLL)扮演著極為重要的角色，主要的功能是產生一固定的頻率，使收發機能傳送/接收正確的訊號且降低雜訊影響。PLL內部包含了相位偵測器(PFD)、充電幫浦(CP)、迴路濾波器(LF)、壓控振盪器(VCO)、除頻器(FD)，而為了追求低功耗，低相位雜訊，與較寬的除頻範圍，在這其中又以壓控振盪器和注入鎖定除頻器特性最重要，而本論文主要研製鎖相迴路之注入鎖定除頻器。

首先，我們探討一個寬頻除三注入鎖定除頻器的鎖頻範圍特性，此除頻器使用台積電矽鍺0.18 μm製程，晶片面積為0.859 × 0.817 mm2。此除三除頻器設計基於一電容耦合的壓控振盪器，且利用電阻加入共振腔來增加除頻範圍。此除頻器最佳工作電壓操作在0.8伏特，整體功耗為5.26 mW，在注入強度為0 dbm時，除頻範圍可從6.2 GHz ~ 12.6 GHz，百分比為68.09 %。此除頻器在一般電壓操作下有很大的鎖頻範圍，然而，當電晶體閘極電壓提高時，此除頻器出現三個不重疊的鎖頻範圍，這現象代表原始設計的除頻器內有更多個共振腔的存在。

其次，我們提出一個高注入功率(> 0 dBm)的除三注入鎖定除頻器的鎖頻範圍特性，此除頻器使用nMOS的交叉偶合架構來產生負阻抗抵銷共振腔的能量損耗，並使用台積電0.18 μm製程進行下線。量測其鎖頻範圍，當注入功率增加時會發生飽和現象而導致鎖頻範圍下降，最後甚至使電路無法正常工作。

第三，提出另外一個高注入功率(> 0 dBm)的除三注入鎖定除頻器的鎖頻範圍特性，此除頻器使用線性的混波器且使用台積電0.18 μm製程製作。模擬顯示當注入功率增加時會發生飽和現象而導致鎖頻範圍下降，甚至讓電路無法工作。但量測時因儀器限制了最高注入功率，並沒有發現飽和的現象。對此我們只能透過公式來驗證，就是模擬當注入功率提高時，電晶體的電流比值與鎖頻範圍的關係。

最後，我們從三個不同架構的除三除頻器去探討高功率的注入訊號對於除頻器電路的影響，並配合公式來模擬和驗證此特性是否正確，以一個積體電路設計者的角度來看，這研究是非常實用的，當你知道高功率注入的特性，在設計階段就可以避免除頻器因注入功率過高時而發生的飽和現象，這也是本篇論文最大的研究貢獻。

Phase Lock Loop (PLL), the most important role in radio frequency (RF) communication system, generates fixed frequency for transceiver, so that the transceiver can transmit/receive the correct signal and reduce the impact of noise. PLL consists of Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF),Voltage Controlled Oscillator (VCO), and Frequency Divider (FD). In order to pursue low-power, low phase noise and wide locking range: the most important characteristics of performance of VCO and Divider, this thesis presents the design of Injection-Locked Frequency Dividers (ILFDs).

First, we discuss the locking range property of a CMOS wide locking range divide-by-3 injection-locked frequency divider (ILFD), this chip uses standard 0.18 μm BiCMOS process and die area is 0.859 × 0.817 mm2. The ILFD circuit bases on capacitive cross-coupled oscillator and uses dual-resonance RLC resonator with resistor to enhance the locking range. The power consumption of the ILFD core is 5.26 mW and the locking range is from 6.2 to 12.6 GHz (68.09%) at injection power Pinj = 0 dBm. The dual-resonance ILFD has wide locking range in normal operation with reasonable power consumption. However, the dual-resonance ILFD has three non-overlapped locking ranges for the ILFD biased at higher gate bias for the switching FETs and subject to high injection power. This indicates that the originally designed ILFD using multi-resonance resonator have three non-overlapped locking ranges of a triple-resonance ILFD.

Secondly, we present the RF locking range of divide-by-3 injection-locked frequency dividers (ILFDs) subjected to high injection power larger than 0 dBm. The divide-by-3 ILFD bases on a push-push cross-coupled n-core MOS LC-tank oscillator and uses linear mixer and was implemented in 0.18 μm CMOS process. The locking range can saturate at high injection power and then starts decreasing as injection power further increases. Finally the ILFD stops tracking the injection source.
Thirdly, we propose the RF locking range of divide-by-3 injection-locked frequency dividers (ILFDs) subjected to high injection power larger than 0 dBm. The divide-by-3 ILFD uses nonlinear mixer and was implemented in 0.18 μm CMOS process. Simulation shows the locking range saturates at high injection power and then starts decreasing as injection power further increases. Finally the ILFD stops tracking the injection source. Measurement shows no saturation of locking range, and this is limited by the measurement set-up.

Finally, we study the high-power injection effect of frequency divider from three different architecture divide-by-3 dividers. This measurement result was verified by simulation. The research is very practical for circuit designer, they can avoid saturation phenomenon by higher power injection at design process. This is the largest contribution of my thesis.

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