簡易檢索 / 詳目顯示

回結果列表
研究生： 廖紫廷
Tzu-Ting Liao
論文名稱： 基於HEVC之可調式搜尋範圍運動估計演算法及高效能電路架構設計
The Algorithm and VLSI Architecture of a High-Throughput Motion Estimation with Adaptive Search Range for HEVC Systems
指導教授： 沈中安
Chung-An Shen
口試委員: 阮聖彰
Shanq-Jang Ruan
郭景明
Jing-Ming Guo
林昌鴻
Chang-Hong Lin
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2016
畢業學年度： 104
語文別： 英文
論文頁數： 51
中文關鍵詞： 高效率視訊編碼 、高吞吐量 、運動估計系統 、可變動搜尋範圍
外文關鍵詞： High Efficiency Video Coding (HEVC), High-Throughput, Motion Estimation, Adaptive Search Range
相關次數： 點閱：348  下載：2 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  •  上一筆

    • 隨著數位影像及網路技術不斷的提升，數位影像在日常生活中無所不在，欲追求影像的細緻度與保持完整的細節，數位影像的解析度大幅提升。為了支援超高畫質影片，例如：4K、8K解析度，與傳輸的限制，新一代視訊壓縮標準High Efficiency Video Coding (HEVC)於2013年發布，與前代AVC相比，在相同的壓縮品質下位元率減少了50%。其中，在整體編碼過程中，運動估計系統占整體編碼時間高達80%。
    本篇論文基於超大型積體電路實現高效率視訊編碼系統中的運動估計，並利用演算法的改良與硬體加速達成高吞吐量之目標。為了支援超高畫質解析度，本論文提出可變動搜尋範圍演算法以減少運算複雜度進而提升系統速度。在相同編碼樹單元(CTU)內，所有包含的預測單元(PU)皆在相同的搜尋範圍內進行運算。而此搜尋範圍的大小是以編碼樹單元的運動估測(MVPLCU)得來的，並且可以依據影像特性改變搜尋範圍的大小，換句話說，本論文提出的方法在影像運動較快時採用較大的搜尋範圍以維持壓縮品質；在影像運動較慢時採用較小的搜尋範圍以降低運算量來提升系統速度。實驗結果顯示出在ㄧ個CTU情況下，平均需要搜尋的候選點數量為160個，相較於搜尋範圍固定為32的全域搜尋演算法，候選點的數量下降96.2%，且平均下降的壓縮品質為0.05 dB。
    在接下來的文章中，我們將詳細的介紹所提出的可變動搜尋範圍演算法與運動估計的硬體架構。本設計基於台積電90奈米製程的環境下實現，pre-layout的結果顯示，在211 MHz的工作頻率下，本設計可以以每秒60張的速度處理4096×2160像素的資料，且所消耗的邏輯閘數量為274.5K個。與前人研究相比，本論文基於提出的演算法之架構實現能達到最大的硬體使用率。

    This thesis presents the VLSI architecture and an efficient algorithm of a high-throughput Motion Estimation (ME) for High Efficiency Video Coding (HEVC) systems. In order to support Ultra High-Definition videos, the system throughput is increased by proposed adaptive search range Algorithm that can reduce the computational complexity while performing Sum of Absolute Difference (SAD) circuits. The variable block sizes within a CTU perform ME in a shared search window and the size of search range is estimated by the MVP of LCU and is inherently adaptive to the characteristic of the video content. Specifically, in the proposed approach, the search window is enlarged for fast motion video and will be shrunk for slow motion video. The statistical results show that the average search candidates of the proposed search range is 160 for a CTU. This leads to 96.2% reduction of search candidates with only 0.05 dB drop in average peak signal-to-noise ratio (PSNR) [25] compared to the conventional 32 full-search example.
    The proposed design is based on TSMC 90nm technology and the pre-layout area complexity is 274.5 KGE and the memory usage is 8 KB. With co-design of algorithm and architecture, the proposed design can achieve resolution of 4096×2160 with 60 frames per second (fps) under 211 MHz. Comparing to the related works, the proposed design can achieve the highest hardware-efficiency.

    摘要 II Abstract III 誌謝 IV Table of Contents V Figures VII Tables VIII I. Introduction 1 II. Background and Related Works 4 2.1 HEVC Basics 4 2.2 Introduction of Motion Estimation 6 2.3 Related Works 8 III. The Proposed Algorithm 11 3.1 Basic Concept and Overview 11 3.2 Proposed Algorithm with Adaptive Search Range 12 IV. VLSI Architecture of Proposed ME 19 4.1 A High-level Overview of the Design 19 4.2 Search Range Decision 21 4.3 Address Generator 22 4.4 Cur./Ref. Buffer 22 4.5 Processing Element 24 4.6 SAD Combinational Tree 25 4.7 SAD Comparator 26 4.8 Best Matching MVD and SAD Buffer 26 V. Experimental Results 27 5.1 PSNR Performance of Proposed Adaptive Search Range 27 5.2 Computational Complexity Analyses 28 5.3 Timing Analysis 30 5.4 Analysis of Total Bandwidth Requirement and System Throughput with Proposed Algorithm 32 5.5 Implementation Results 35 5.6 Comparisons with Prior Arts 36 VI. Conclusion 39 References 40

    [1] G. J. Sullivan, J.-R. Ohm, W. J. Han, and T. Wiegand, “Overview of the High Efficiency Video Coding (HEVC) standard,” IEEE Trans. Circuits System Video Technology, vol. 22, no. 12, pp. 1648–1667, Dec. 2012.
    [2] M. E. Sinangil, V. Sze, M. Zhou, A. P. Chandrakasan, “Memory Cost vs. Coding Efficiency Trade-Offs for HEVC Motion Estimation Engine,” IEEE International Conference on Image Processing, pp. 1533-1536, Sep. 2012.
    [3] M. Grellert, M. Shafique, M. U. Karim Kha, L. Agostini, J. C. B. Mattos and J. Henkel, “An Adaptive Workload Management Scheme for HEVC Encoding,” IEEE International Conference on Image Processing, vol. 1, pp.1850-1854, Sep. 2013
    [4] I.-K. Kim, J. Min, T. Lee, W.-J. Ham and J. Park, “Block Partitioning Structure in the HEVC Standard,” IEEE Trans. Circuits and Systems for Video Technology, vol. 22, no, 12, pp.1697-1706, Dec. 2012.
    [5] M. T. Pourazad, C. Doutre, M. Azimi and P. Nasiopoulos, “HEVC: The New Gold Standard for Video Compression: How Does HEVC Compare with H.264/AVC?,” IEEE Consumer Electronics Magazine, vol. 1, pp. 36-46, Jul. 2012.
    [6] “JCT-VC Reference Software HM-10.1,” ISO/IEO MPEG and ITU-T.
    [7] C.-H. Cheung, “Novel Cross-diamond-hexagonal Search Algorithms for Fast Block Motion Estimation,” IEEE Trans. Multimedia, vol. 7, pp. 16-22, Feb. 2002.
    [8] Z. Xin and Z. Wei, “A Fast Mixed Integer-pixel Search Algorithm Based on Centered Prediction for H.264,” IEEE International Conference on Computer Science and Information Technology, vol. 9, pp. 214-217, Jul. 2010.
    [9] X. Li, R. Wang, W. Wang, Z. Wang and S. Dong, “Fast Motion Estimation Methods for HEVC,” Broadband Multimedia Systems and Broadcasting, Vol. 1. pp. 1-4, Jun. 2014.
    [10] M. E. Sinangil, A. P. Chandrakasan, V. Sze and M. Zhou, “Hardware Motion Estimation Search Algorithm Development for High Efficiency Video Coding (HEVC) Standard,” IEEE International Conference on Image Processing, pp. 1529-1532, Sept. 2012.
    [11] S. Y. Jou, S. J. Chang and T. S. Chang, “Fast Motion Estimation Algorithm and Design for Real Time QFHD High Efficiency Video Coding,” IEEE Trans. Circuits and Systems for Video Technology, vol. 25, pp. 1533-1544, Sep. 2015.
    [12] Y.-W. Huang, T.-C. Wang, B.-Y. Hsieh and L.-G. Chen, “Hardware Architecture Design for Variable Block Size Motion Estimation in MPEG-4 AVC/JVT/ITU-T H.264,” in Proceedings of International Symposium on Circuits and Systems, vol. 2, pp. 796-799, May. 2003.
    [13] Y. Xu, J. Liu, Z. Zhang and R. K. F. Teng, “A High Performance VLSI Architecture for Integer Motion Estimation in HEVC,” IEEE International Conference on ASIC, pp. 1-4, Oct. 2013.
    [14] J. Zhou, D. Zhou, G. He and S. Goto, “A 1.59Gpixel/s motion estimation processor with −211-to-211 search range for UHDTV video encoder,” IEEE International Symposium on VLSI Circuits, pp. C286–C287, Jun. 2013.
    [15] S. M. Reza Soroushmehr, S. Samavi and S. Shirani, “Simple and Efficient Motion Estimation Algorithm by Continuum Search,” Springer Journal of Multimedia Tools and Applications, vol. 71, pp. 1615-1633, Aug. 2014.
    [16] S. Kim, D.-K. Lee, C.-B. Sohn and S.-J. Oh, “Fast Motion Estimation for HEVC with Adaptive Search Range Decision on CPU and GPU,” IEEE International Conference on Signal and Information Processing, pp. 349–353, Jul. 2014.
    [17] A. Medhat, A. Shalaby, M. S. Sayed, M. Elsabrouty and F. Mehdipour, “Fast Center Search Algorithm with Hardware Implementation for Motion Estimation in HEVC Encoder,” IEEE International Conference on Electronics Circuits and Systems, pp. 155-158, Dec. 2014.
    [18] G.-L. Li, C.-C. Wang and K.-H. Chiang, “An Efficient Motion Vector Prediction Method for Avoiding AMVP Data Dependency for HEVC,” IEEE International Conference on Acoustic, Speech and Signal Processing, pp. 7363–7366, May. 2014.
    [19] G. A. Ruiz and J. A. Michell, “An Efficient VLSI Processor Chip for Variable Block Size Integer Motion Estimation in H.264/AVC,” Signal Processing Image Communication, vol. 26, pp.289-303, Apr. 2011
    [20] J. Byun, Y. Jung and J. Kim, “Design of Integer Motion Estimator of HEVC for Asymmetric Motion-partitioning Mode and 4K-UHD,” IEEE Electronics Letters, vol. 49, pp.1142-1143, Aug. 2013.
    [21] J.-C. Tuan, T.-S. Chang and C.-W. Jen, “On the Data Reuse and Memory Bandwidth Analysis for Full-search Block-matching VLSI Architecture,” IEEE Trans. on Circuits and Systems for Video Technology, vol. 12, pp. 61-72, Jan. 2002.
    [22] P. Nalluri, L. N. Alves and A. Navarro, “A Novel SAD Architecture for Variable Block Size Motion Estimation in HEVC Video Coding,” IEEE International Symposium on System on Chip, pp. 1-4, Oct. 2013.
    [23] G. Bjontegaard, “Calculation of Average PSNR Differences between RD-curves,” document VCEG-M33, ITU-T SG16 Q.6 Video Coding Experts Group, Apr. 2001.
    [24] Ultra-high-definition Video Group, Test Sequences: (Online).
    https://media.xiph.org/video/derf/ (2015). Accessed 2 Feb. 2015.
    [25] T. K. Tan, R. Weerakkody, M. Mrak, N. Ramzan, V. Baroncini, J.-R. Ohm and G. J. Sullivan, “Video Quality Evaluation Methodology and Verification Testing of HEVC Compression Performance,” IEEE Trans. on Circuits and Systems for Video Technology, Vol. 26, pp. 76–90, Jan. 2016.

    QR CODE