隨著科技的日新月異，頻率合成器在現今社會中已佔據不可或缺的角色，許多產品都需要有高速傳輸的功能，不外乎有除頻器、倍頻器、以及VCO，這些都是追求低功耗、高倍頻範圍、以及低相位雜訊重要的指標，本文分成三大部分，分別為應用於雙頻架構的三倍頻器以及兩顆經由不同耦合方式的四相位VCO。晶片使用tsmc 0.18-μm CMOS mixed-signal and RF 1P6M technology和tsmc 0.18-μm BICMOS mixed-signal SiGe general purpose standard process FSG Al 3P6M 1.8&3.3V製程工藝製作。
第一部分為雙頻架構的注入鎖定三倍頻器，晶片面積為0.901 × 1.2 mm2，利用雙端注入產生一倍諧振經由兩顆n型電晶體源極之間串接一電感產生二倍頻率輸出，最後由汲極輸出三倍頻訊號。此電路利用兩顆n型電晶體交叉耦合形成負阻抗。在總偏壓1.2 V、調頻電壓為0 V時自振頻率為3.78 GHz、調頻電壓為2 V時自振頻率為5.47 GHz，功耗約為12.036 mW，當輸入訊號功率為 0 dBm 時，兩自振頻率疊加輸入端注入鎖定的頻率範圍為0.67 GHz至2.33 GHz，並在輸出端產生頻率範圍從2 GHz至7 GHz (111.1%) 的訊號。
第二部分為利用電感串接耦合實現的考畢子QVCO，本架構由兩組p型電晶體交叉耦合VCO構成。晶片面積為1.124 × 1.2 mm2。在1.2 V供應電壓，功耗為3.7523mW，可調節頻率範圍為4.6 GHz至5.07 GHz。當頻率為4.59 GHz時，VCO的相位雜訊在1 MHz的頻率偏移下為 -122.72 dBc/Hz、FOM值為 -190.21 dBc/Hz。
最後一部分設計了雙邊完全對稱之八字電感。此架構結合各一個p、n型電晶體產生負電阻，加上兩個可調節頻率之可變電容，本架構由四組子VCO所組成，並使用四組變壓器連接形成封閉式傳輸線，以耦合四個子震盪器。當提供電源為1.2 V時，功耗為5.84 m.W，可調節頻率範圍為8.536 GHz至10GHz。當頻率為8.536 GHz時，VCO的相位雜訊在1 MHz的頻率偏移下為 -122.4 dBc/Hz、FOM值為 -193.4 dBc/Hz。晶片面積為1.2 × 1.2 mm2。

With the rapid advancement of technology, frequency synthesizers have become essential in today's society. Many products require high-speed transmission capabilities, including dividers, multipliers, and VCOs. These components are crucial for achieving low power consumption, high-frequency multiplication range, and low phase noise. This paper is divided into three parts, including a multiplier for dual-frequency architecture and two quadrature VCOs using different coupling methods. The chips were fabricated using the TSMC 0.18-μm CMOS mixed-signal and RF 1P6M technology and the TSMC 0.18-μm BICMOS mixed-signal SiGe general-purpose standard process FSG Al 3P6M 1.8&3.3V process technology.
The first part is a 3x injection-locked multiplier for dual-frequency architecture, with a chip area of 0.901 × 1.2 mm². It utilizes double-ended injection to generate a doubled resonant frequency through two N-type transistors connected in series between the source and an inductor and finally outputs a tripled frequency signal from the drain. This structure uses two N-type transistors cross-coupled to form a negative resistance. At a total bias voltage of 1.2 V and tuning voltage of 0 V, the self-oscillation frequency is 3.78 GHz, and at a tuning voltage of 2 V, the self-oscillation frequency is 5.47 GHz. The power consumption is approximately 12.036 mW. When the injection signal power is 0 dBm, the frequency range for injection locking of the combined self-oscillation frequencies at the input is 0.67 GHz to 2.33 GHz, and the output signal has a frequency range from 2 GHz to 7 GHz (111.1%).
The second part is a Colpitts quadrature voltage-controlled oscillator (QVCO) implemented using inductive coupling. This structure consists of two sets of P-type transistor cross-coupled VCOs. The chip area is 1.124 × 1.2 mm². At a supply voltage of 1.2 V., the power consumption is 3.7523 mW, and the frequency range is adjustable from 4.6 GHz to 5.07 GHz. At a frequency of 4.59 GHz, the p.ha.se noise of the VCO is -122.72 dBc/Hz at a 1 MHz frequency offset, and the FOM value is -190.21 dBc/Hz.
The final part presents the design of a fully symmetrical eight-shaped inductor structure. This structure combines one P-type and one N-type transistor to generate negative resistance and two adjustable frequency variable capacitors. The structure consists of four sub-VCOs and uses four transformers connected to form a closed-loop transmission line to couple the four sub-oscillators. At a supply voltage of 1.2 V, the power consumption is 5.84 mW, and the frequency range is adjustable from 8.536 GHz to 10 GHz. At a frequency of 8.536 GHz, the phase noise of the VCO is -122.4 dBc/Hz at a 1 MHz frequency offset, and the FOM value is -193.4 dBc/Hz. The chip area is 1.2 × 1.2 mm².

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