本論文實現一個十位元、每秒一億六千萬次取樣之逐漸逼近式類比數位轉換器。為了加速這個類比數位轉換器的操作速度，它使用了一個利用比較器輔助之逐漸逼近式架構。為了避免在它的數位類比轉換器中，使用過大的電容陣列來保持十位元所需的線性度。我使用了一個電容交換技術，使整體電容值可以滿足雜訊要求為限制。為了抵抗對製程、電壓與溫度之變異，本論文使用一個適應性取樣機制。

This thesis presents a 1.2-V 10-bit 160-MS/s successive approximation register (SAR) analog-to-digital converter (ADC). A comparator-assisted SAR (CA-SAR) ADC architecture is proposed to speed up the ADC operation. To maintain the 10-bit linearity requirement without using a large total capacitance in the capacitive digital-to-analog converter (C-DAC), a capacitor-swapping scheme is used to implement C-DAC for thermal noise limitation. In order to against process, voltage and temperature variations, a adaptive sampler is proposed in this thesis.

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