在本論文是介紹一個如何在CMOS 65奈米製程下，實現一個八位元每秒十二億五千萬次取樣的類比至數位轉換器，其是採用次階-連續漸進式為架構；供應電壓為1.2伏特，輸入信號的全範圍為1.2伏特。當輸入頻率為六百兆赫時，信號對雜訊與失真比(SNDR)為46dB，無雜散信號動態範圍(SFDR)為59dB，整體的消耗功率為19.2毫瓦。
能夠達到高速的操作是藉由以下幾點來實現，也是本論文的重點，第一是我們的粗略類比至數位轉換器採用了轉換時間最短的快閃式架構，第二個是我們的精確類比至數位轉換器採用兩個通道的連續漸進式架構，藉由時間交錯的方式來使得轉換時間得以緩解，第三則是我們在電容數位至類比轉換器的部分採用了單調式切換搭配共模電壓抬高的切換方式，使得比較器的輸入電壓在較高的準位，進而降低轉換的時間延遲。
由於快閃式架構是由比較器為主體所組成的電路，為了要達到一定的精確度，比較器的消耗功率勢必相當可觀，且要產生給比較器使用的參考電壓的電阻串，其靜態消耗功率也會造成整體電路消耗功率的提高，為了解決這兩個問題，我們採用了內建參考電壓的比較器，且使用栓鎖器插值法降低比較器的數量。而我們在精確類比至數位轉換器使用兩通道，而兩通道則會引入時間歪斜的問題，我們採用了主取樣的技術降低時間歪斜造成的錯誤。

粗略類比至數位轉換器所採用的內建參考電壓的比較器以及兩通道之間的精確類比至數位轉換器的比較器皆採用前景校正的方式來確保因不匹配所造成的抵補電壓。

This thesis introduces how to design and implement an 8-bits 1.25-GS/s analog-to-digital converter (ADC) in the 65nm CMOS process. In this work, the Subranged-SAR architecture is used. The supply voltage is 1.2V. When the input frequency is 600MHz, the Signal to Noise and Distortion Ratio (SNDR) is 46 dB, and the Spur-Free Dynamic Range (SFDR) is 59 dB, the power consumption is 19.2 mW.

The high speed operation can be achieved is by following, also the thesis focus, (1) the coarse ADC (CADC) uses the most fast architecture is the flash architecture, (2) the fine ADC (FADC) uses two channel Successive-Approximation (SAR) ADC with the time-interleaved architecture to alleviate the conversion time, (3) in our FADC, the main DAC (MDAC) uses the set-and-down switching with common-mode boosting to make the input voltage of comparator (CMP) can be risen to higher level, and then cut down the conversion delay time.
Because the flash architecture is composed by CMPs, in order to achieve the accuracy requirement, the CMP’s power consumption will be considerable. To generate a reference voltage of the CMP, a resistor string is applied. Its static power consumption also increases the total power consumption. To solve these two power issues, I choose the CMP with a built-in reference voltage. Moreover, I use the latch interpolation to decrease the CMP amount by half. The FADC uses two ADC channels to save time. It will introduce a timing-skew problem. In this work, the master sampling technique was applied to reduce the errors caused by the timing skew.

The built-in reference voltage of CMPs is calibrated in the foreground to make sure the offset voltages are compensated.

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