本論文提出低功耗高線性度可編程重組化高階濾波器，可應用於生醫感測類比前端電路中，以去除非頻帶之訊號以及雜訊。本論文所實現之高階濾波器響應可由多個可編程重組化之二階轉導電容濾波器串接而成，每個二階轉導電容濾波器包含四個線性化之轉導運算放大器以及兩個電容，並可視需求產生低通或帶通之輸出響應。
為了增進濾波器之線性度，所設計之轉導運算放大器差動對使用六組擴散對及四組差動對以非線性相消的方式擴增電路之輸入線性範圍。為了更加提升電路之功率效能及提供轉導值之編程性，轉導運算放大器電路使用全差動架構，利用懸浮閘電晶體調控轉導運算放大器之電流值及實現共模回授，並使用互補差動對使轉導值能夠在相同電流下倍增。為了降低並減少製程變異對線性度的影響，電路佈局使用共質心布局技巧，同時考慮不同電晶體電流之敏感度以決定電晶體之尺寸，不同尺寸之電晶體利用單一尺寸電晶體以串聯或並聯方式組成。由電路模擬結果可知，在相同電路頻寬條件下，與原始基本之轉導運算放大器相比，所提出之轉導運算放大器電路功耗增加57%，輸入等效雜訊增加19%，但是輸入線性範圍可改善17.71倍。
利用所設計之轉導運算放大器所構成之二階轉導電容濾波器中，可透過編程轉導運算放大器之電流來調整放大器之中心頻率、增益、及品質因數等參數，並使用一內含非揮發性記憶體之串並列傳輸電路設定訊號輸入及輸出之路徑，並得以選擇低通或帶通輸出。所提出之濾波器電路以台積電0.35m標準CMOS製程設計並實現，量測結果得知，轉導運算放大器之輸入線性範圍可達216mVpp，二階低通輸出之等效輸入雜訊為86Vrms，當頻寬編程為2kHz時，所需之功耗為100nW，無雜波動態範圍為52.6dB。相同中心頻率下，帶通輸出之等效輸入雜訊為72.9Vrms，無雜波動態範圍為53.57dB。此外，為了增加輸入線性範圍，本論文也提出使用輸入電容衰減技術，並利用可編程高阻抗虛擬電阻，給定懸浮節點初始電壓，使雙端輸入線性範圍增加至0.9Vpp(0.636Vrms)，可得到之動態範圍59.4225dB。
本論文最後討論轉導電容濾波器設計參數內轉導放大器轉導值會受到溫度飄移展生變化，進而影響濾波器之參數，因此本論文設計一轉導放大器轉導值之溫度補償電路，就能降低轉導放大器受到溫度的影響進而降低濾波器之參數變化。由量測可得知，由常溫27度至80度，有溫度補償之四階低通切比雪夫濾波器其截止頻率變化量，由無溫度補償之1649%降至91.5%，其變化量相差18倍。

In this thesis, a low-power high linearity programmable high-order filter is designed and presented that is suitable to be employed in the analog front-end circuitsfor biomedical applications to remove out-of-band signals and interference. This filter consists of a cascade of multiple reconfigurable biquadratic sections that can provide lowpass or bandpass responses.The reconfigurable biquadratic section is composed of four power-efficient linearized operational transconductance amplifiers (OTAs) and two capacitors with all filter parameters, such as the natural frequency, gains, and quality factor, orthogonally programmable.
The differential pair in the proposed OTA is composed of six differs and four differential pairs so that nonlinearity cancellation technique can be applied to improve OTA input linear range. To further improve power efficiency, complementary differential pair topology as well as current reuse technique is employed to double the transconductance value under the same condition of current consumption. Floating gate transistors are used to adjust the bias current of the OTA and to implement the common-mode feedback without extra power consumption. To minimize the impact of process variation, common-centroid layout techniques are applied. The transistor dimensions are designed according to the component sensitivity. Each transistor is realized by series or parallel combination of unit size transistors. From simulation, compared with a basic OTA under the same condition of bandwidth requirement, the power consumption of the proposed OTA increases by 57% and the input referred noise increases by 19%. However, the input linear range can be improved by 17.71 times.
A high-order filter chip that is composed of six proposed OTA-C filter is designed and fabricated in TSMC 0.35m CMOS process. The gains, natural frequency, and quality factor of each biquadratic filter can be orthogonally programmed. A serial-peripheral interface circuit with non-volatile memory is used to select the signal path as well as lowpass or bandpass output. From measurements, the input linear range of the OTA can be 216mVpp. The input referred noise from the lowpass output is 86Vrms.When the bandwidth is programmed at 2kHz, the power consumption is 100nW with spurious-free dynamic range (SFDR) of 52.6dB. With the same natural frequency, the measured input referred noise from the bandpass output is 72.9Vrms and the measured SFDR is 53.57dB. Besides, to further increase the input linear range, this thesis also propose another linearization technique using capacitive input attenuation technique with programmable high impedance pseudo-resistors. In this manner, the input linear range can be improved to 0.9Vpp with SFDR of 59.42dB.
Finally, this thesis designs a temperature compensation circuit containing a PTAT circuit to reduce the effect of temperature drift. From measurement, the frequency drift can reduced from 1649% to 91.5% when temperature drifts from 27〬C to 80〬C.

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