隨著影視與音樂產業的蓬勃發展，高解析度類比/數位轉換器的需求量以及重要性也日益提升。在聲頻應用的CD片，其規格為：16位元及取樣頻率44.1 kHz，要做到如此高的解析度，選用三角積分調變的類比/數位轉換器是再適合不過的了。
　　本論文針對三角積分調變類比/數位轉換器中的三角積分調變器進行設計，規格以CD音質為目標。三角積分調變器是以Sturdy-MASH架構為基礎進行改良，並稱之為Hybrid Sturdy-MASH。在電路設計的部分，採用全差動式放大器以抑制偶次諧波；巧妙運用正、反相積分器以消除第一級量化雜訊，並達成三至四階雜訊移頻的效果；將量化器提升至1.5位元以降低量化雜訊，藉此來提升整體系統的解析度。
　　本篇論文所設計之晶片採用TSMC 0.18-μm CMOS製程，供應電壓為1 V， 晶片總功率消耗2.66 mW，總面積為1.892 mm^2。系統頻寬為24 kHz，取樣頻率為4.608 MHz，故超取樣率為96倍。最終晶片量測SNDR達76.01 dB，換算等效位元數(ENOB)為12.33位元。

　　With the vigorous development of the film and music industry, the demand of high-resolution analog/digital converters (ADC) is also increasing. The specifications of CD discs for audio applications are: a 44.1 kHz sampling rate and a 16 bit resolution. Among several ADC architectures, the delta-sigma modulation is suitable for CD-quality audio applications.
　　This thesis presents a discrete time delta-sigma modulator. The goal of this research is to achieve a CD quality modulator. The delta-sigma modulator is improved based on the Sturdy-MASH architecture and is called a Hybrid Sturdy-MASH modulator. In the circuit design part, a fully differential amplifier is used to suppress even-mode harmonics. Ingeniously using inverting integrator and non-inverting integrator to eliminate the first-stage quantization noise, the proposed DSM achieves a third to fourth order noise shaping. The quantizer is increased to 1.5 bits to reduce the overall quantization noise, thereby improving the resolution of the whole system.
　　The proposed circuit is designed and realized in TSMC 0.18-μm CMOS technology. The supply voltage is 1 V and the power consumption of the chip is 2.66 mW. The overall layout area is 1.892 mm^2, the system bandwidth is 24 kHz, the sampling frequency is 4.608 MHz, and the oversampling ratio is 96. The measured signal-to-noise-and-distortion-ratio (SNDR) is 76.01 dB, so the equivalent number of bits (ENOB) is 12.33 bits.

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