預先計算內容可定址記憶體(Pre-computation-Based Content Addressable Memory, PB-CAM)是一種能夠減少內容可定址記憶體在進行資料比對時所需要的比對次數，進而達到節省功率目的的方法，但先前的研究大多著重在特徵值所能達成的過濾比率，卻都忽略了電路架構中會產生短路功耗的缺陷。
本論文提出一個針對預先計算內容可定址記憶體短路功耗改良的CMOS比較電路架構。此架構最大的特點在於採用CMOS邏輯閘當作比較器，如此可以避免掉傳統架構在特徵值吻合，但實際值不吻合時所產生的短路電流。
我們在台積電0.18μm的製程下，利用Spice去實現整個預先計算內容可定址記憶體的硬體設計，並使用Nanosim去模擬整個系統的功率消耗。實驗結果顯示，在一個容量大小為128×32之內容可定址記憶體下，相較於其他Pseudo-NMOS架構的預先計算內容可定址記憶體，我們提出的CMOS架構可以節省37.67％的功率消耗。
這篇論文最主要的貢獻在於點出當預先計算內容可定址記憶體進行資料比對時，短路功耗對整體功耗的影響，並且提出可以改善Pseudo-NMOS架構中短路情況的CMOS比較電路。

Pre-computation-based content-addressable memory (PB-CAM) is one of the methods to reduce the number of comparison operations during the search cycle.
Previous researches had focused on the filtering rate of the parameter extractor for low power, but ignored the short-circuit drawback of this architecture.

In this thesis, an improved comparison circuit for pre-computation-based content-addre-ssable memories (PB-CAMs) is presented.
We also compared the power consumption of four low-power PB-CAMs.
We develop a new PB-CAM architecture with a low power consumption parameter extractor and an improved comparison circuit to solve short-circuit problem and further enhance power efficiency for general purpose applications.

With a 128 words by 32 bits CAM size, the simulation results show that our proposed PB-CAM effectively reduces 37.67% power consumption by employing a proper parameter extractor and improved comparison circuit of the PB-CAM compared with the static pseudo-NMOS architecture.

The major contribution of this thesis is that we analyze the effect of the short-circuit power of pseudo-NMOS during search operation in the CAM and further propose an improved
comparison circuit to reduce the short-circuit power of pseudo-NMOS for PB-CAMs.

[1] S. Swaminathan, S. B. Patel, J. Dieffenderfer, and J. Silberman, “Reducing power
consumption during TLB lookups in a PowerPC embedded processor,” in Proc. Int.
Symp. Quality of Electronic Design (ISQED), Mar. 2005, pp. 54–58.
[2] Y.-J. Chang, “An energy-efficient BTB lookup scheme for embedded processors,”
IEEE Trans. Circuits and Systems II: Express Briefs, vol. 53, pp. 817–821, Sep. 2006.
[3] R. Sangireddy and A. K. Somani, “High-speed IP routing with binary decision dia-
grams based hardware address lookup engine,” IEEE J. Selected Areas in Communi-
cations, vol. 21, pp. 513–521, May 2003.
[4] Y.-J. Chang and Y.-H. Liao, “Hybrid-type CAM design for both power and perfor-
mance efficiency,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 16,
pp. 965–974, Aug. 2008.
[5] F. Shafai, K. J. Schultz, G. F. R. Gibson, A. G. Bluschke, and D. E. Somppi, “Fully
parallel 30-MHz, 2.5-Mb CAM,” IEEE J. Solid-State Circuits, vol. 33, pp. 1690–
1696, Nov. 1998.
[6] G. Thirugnanam, N. Vijaykrishnan, and M. J. Irwin, “A novel low power CAM de-
sign,” in Proc. IEEE Int. ASIC/SOC Conf., Sep. 2001, pp. 198–202.
37
38
[7] K.-H. Cheng, C.-H. Wei, and Y.-W. Chen, “Design of low-power content-addressable
memory cell,” in Proc. IEEE Int. Midwest Symp. Circuits and Systems (MWSCAS),
vol. 3, Dec. 2003, pp. 1447–1450.
[8] C.-S. Lin, J.-C. Chang, and B.-D. Liu, “A low-power precomputation-based fully
parallel content-addressable memory,” IEEE J. Solid-State Circuits, vol. 38, pp. 654–
662, Apr. 2003.
[9] S.-J. Ruan, C.-Y. Wu, and J.-Y. Hsieh, “Low power design of precomputation-based
content addressable memory,” IEEE Trans. Very Large Scale Integration (VLSI) Sys-
tems, vol. 16, no. 3, pp. 331–335, Mar. 2008.
[10] K.-H. Cheng, C.-H.Wei, and S.-Y. Jiang, “Static divided word matching line for low-
power content addressable memory design,” in Proc. IEEE Int. Symp. Circuits and
Systems (ISCAS), vol. 2, May 2004, pp. 629–632.
[11] H. Miyatake, M. Tanaka, and Y. Mori, “A design for high-speed low-power CMOS
fully parallel content-addressable memory macros,” IEEE J. Solid-State Circuits,
vol. 36, pp. 956–968, Jun. 2001.
[12] I. Arsovski, T. Chandler, and A. Sheikholeslami, “A ternary content-addressable
memory (TCAM) based on 4T static storage and including a current-race sensing
scheme,” IEEE J. Solid-State Circuits, vol. 38, pp. 155–158, Jan. 2003.
[13] I. Arsovski and A. Sheikholeslami, “A mismatch-dependent power allocation tech-
nique for match-line sensing in content-addressable memories,” IEEE J. Solid-State
Circuits, vol. 38, pp. 1958–1966, Nov. 2003.
[14] Y.-L. Hsiao, D.-H. Wang, and C.-W. Jen, “Power modeling and low-power design
of content addressable memories,” in Proc. IEEE Int. Symp. Circuits and Systems
(ISCAS), vol. 4, May 2001, pp. 926–929.
39
[15] A. Efthymiou and J. D. Garside, “A CAM with mixed serial-parallel comparison for
use in low energy caches,” IEEE Trans. Very Large Scale Integration (VLSI) Systems,
vol. 12, pp. 325–329, Mar. 2004.
[16] N. Mohan and M. Sachdev, “Low power dual matchline ternary content addressable
memory,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 2, May 2004,
pp. 633–636.
[17] A. Roth, D. Foss, R. McKenzie, and D. Perry, “Advanced ternary CAM circuits on
0.13 um logic process technology,” in Proc. IEEE Custom Integrated Circuits Conf.,
Oct. 2004, pp. 465–468.
[18] S. Hanzawa, T. Sakata, K. Kajigaya, R. Takemura, and T. Kawahara, “A large-scale
and low-power CAM architecture featuring a one-hot-spot block code for IP-address
lookup in a network router,” IEEE J. Solid-State Circuits, vol. 40, pp. 853–861, Apr.
2005.
[19] ——, “A dynamic CAM-based on a one-hot-spot block code for millions-entry
lookup,” in Symp. VLSI Circuits Dig. Technical Papers, Jun. 2004, pp. 382–385.
[20] S.-J. Ruan, J.-Y. Hsieh, and C.-H. Lee, “Synthesis and design of parameter extractors
for low-power pre-computation-based content-addressable memory,” IEICE Transac-
tions on Electronics (special issue on Hardware and Software Technologies on Ad-
vanced Microprocessors), vol. E92-C, no. 10, pp. 1249–1257, Oct. 2009.
[21] J. Lamoureux, G. G. F. Lemieux, and S. J. E. Wilton, “GlitchLess: dynamic power
minimization in FPGAs through edge alignment and glitch filtering,” IEEE Trans.
Very Large Scale Integration (VLSI) Systems, vol. 16, pp. 1521 – 1534, Nov. 2008.
[22] K. Itoh, “Ultra-low voltage nano-scale embedded RAMs,” in Proc.IEEE North-East
Workshop Circuits and Systems (ISCAS), Jun. 2006, pp. 245 – 248.
40
[23] Y.-T. Pai, C.-H. Lee, S.-J. Ruan, and E. Naroska, “An improved comparison circuit
for low power pre-computation-based content-addressable memory design,” in Proc.
IEEE Int. Conf. on Electronics, Circuits and Systems (ICECS), Dec. 2009, pp. 663–
666.
[24] P. Zhao, J. B. McNeely, P. K. Golconda, S. Venigalla, N. Wang, M. A. Bayoumi,
W. Kuang, and L. Downey, “Low-power clocked-pseudo-NMOS flip-flop for level
conversion in dual supply systems,” IEEE Trans. Very Large Scale Integration (VLSI)
Systems, vol. 17, no. 9, pp. 1196–1202, Sep. 2009.