在我們之前實驗室所提出的論文“浮動累加器架構”（Floating Accumulator architecture）當中，我們提出了一個新穎的架構和新的指令集編碼方式，這個架構可以結合暫存器架構和累加器架構的優點，可以在不增加指令長度並且不犧牲原有功能的情況下，利用到暫存器數量加倍帶來的好處。

但是在之前的論文中，在編譯器的部分做了複雜的修改，使得浮動累加器架構較不易實作，於是我們決定試著將浮動累加器架構實作在組譯器上，在編譯器部分只做必要的修改。

我們將浮動累加器架構實作在組譯器之後，我們分析了造成效能不佳的原因並提出兩種改善方法來減少非必要產生的設定浮動累加器指令數量，可以使未改善的浮動累加器架構減少平均4%的code size，並且改善平均約2.3%的執行時間。

Before we published a paper from our laboratory "float accumulator architecture" (Floating Accumulator architecture), we propose a novel architecture and new instruction set encoding, this architecture can be combined the advantage of the architecture of accumulator and register, it will not increase the length of instruction and without sacrificing the original features, to use the benefits that doubling the number of registers.

But in the previous paper, in parts of the compiler to do a complex modifications, such that the floating accumulator architecture more difficult to implement, so we decided to try to implement the floating accumulator architecture in assembler, compiler section only do the necessary changes.

Then we will implement the floating accumulator architecture in assembler, we analyze the causes of poor performance and propose two improved ways to reduce unnecessary generation of instructions of set floating accumulator that can make original floating accumulator architecture reduces the average 4% of code size, and to improve an average of about 2.3% of the execution time.

[1] ARM Limited. ARM9TDMITM Technical Reference Manual,2000.

[2] Todd Austin, David Blaauw, Scott Mahlke, Trevor Mudge,Chaitali Chakrabarti, and Wayne Wolf. Mobile supercomputers.IEEE Computer, 37(5):81–83, May 2004.

[3] Todd Austin, Eric Larson, and Dan Ernst. SimpleScalar: An infrastructure for computer system modeling. IEEEComputer, 35(2):59–67, 2002.

[4] X. Zhuang, S. Pande. Differential register allocation, In Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation, pages 57-70, 2005.

[5] Edil S. T. Fernandes, Anna Dolejsi Santos, and Claudio L. de Amorim. Conditional execution:An approach for eliminatingthe basic block barriers. Microprocessing and Microprogrammin,40:689–692, 1994.

[6] Chunho Lee, Miodrag Potkonjak and William H.Mangione-Smith MediaBeinch: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems.In Proceeding of MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture Pages 330-335

[7] GCC. The GNU compiler collection. http://gcc.gnu.org/.

[8] Wen-Mei Hwu. Technology outlook: Introduction to predicated execution. IEEE Computer, 31(1):49–50, January 1998.

[9] Intel Corporation. IntelR StrongARM SA-1110 Microprocessor Developer’s Manual, October 2001.

[10] Joseph C. H. Park and Mike Schlansker. On predicated execution. Technical Report HPL-91-58, HP Labs, 1991.

[11] Xiaotong Zhuang, Tao Zhang, and Santosh Pande. Hardwaremanaged register allocation for embedded processors. In Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, pages 192–201, 2004.

[12] Simon Segars. Low power design techniques for microprocessors. In 2001 IEEE International Solid-State Circuits Conference (ISSCC), 2001.

[13] Tokuzo Kiyohara, Scott Mahlke, William Chen, Roger Bringmann, Richard Hank, Sadun Anik, and Wen-Mei Hwu.Register connection: a new approach to adding registers into instruction set architectures. In Proceedings of the 20th annual international symposium on Computer architecture, pages 247–256, 1993.

[14] David Seal, editor. ARM Architecture Reference Manual. Addison-Wesley Professional, 2nd edition, 2001.

[15] Chunho Lee, Miodrag Potkonjak, and William H. Mangionesmith. MediaBench: A tool for evaluating and synthesizing multimedia and communications systems. In Proceedings of the 30th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’97), pages 330–335, 1997.

[16] Huang-Jia Cheng and Yuan-Shin Hwang. Trading conditional execution for more registers on ARM.In Proceedings of the 2010 EUC, pages 53–59, 2010.

[17] Arvind Krishnaswamy and Rajiv Gupta. Efficient use of invisible registers in thumb code. In Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’05), 2005.

[18] J.H. Lee, J. Park, S.M. Moon. Securing More Registers with Reduced Instruction Encoding Architectures. In Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA’07), pages 417-425, 2007

[19]Wei-Che Hsu and Yuan-Shin Hwang. Floating Accumulator Architecture, 2014