本論文目標在於設計生醫應用之時域式類比至數位轉換器，在轉換的過程中會插入部分時域之轉換與應用，相較於傳統電壓量化至數位的方式能達到更好的性能以及更加省電之目的。
本次設計為了達到省電之目的，電路以SAR ADC架構做延伸，電路架構大致可分成：取樣保持電路、時域式比較器、CDAC、循序漸進式控制邏輯與數位斜波充放電及控制單元。首先電路在取樣階段時，取樣保持電路會取樣輸入訊號，進入轉換階段後，時域式比較器會將取樣到的輸入電壓轉換成輸入時間，並比較輸入時間之快慢給出對應的邏輯訊號，CDAC依照給出的邏輯訊號去做對應切換並做下一次之比較，直到完成前十位元之轉換；再者，數位斜波充放電與控制單元會依照最後一次比較結果搭配邏輯控制電路對輸入節點做數位斜波式的充放電，在這期間時域式比較器會一直去比較輸入端換成的時間差值直到輸出邏輯準位與第十次的比較結果不同，這期間數位斜波式的充放電的次數會被記錄下來並解碼，與前面十位元做整合後輸出。
本論文下線晶片使用 TSMC 0.18μm CMOS標準製程實現，整體晶片佈局面積含 I/O pads為1.163×1.013 mm2，操作電壓為1.0V與1.8V，解析度為14位元，20kHz之取樣頻率，訊號對雜訊與失真比(SINAD)為78.63dB，有效位元(ENOB)為12.77bits，Fom為14.3fJ/c-s，電路整體功率消耗為2uW。

he goal of this paper is to design a 14-bit time-domain analog-to-digital converter (TADC) for biomedical applications. Some part of the conversion will be processed in time-domain. Compared with many traditional methods that directly quantize the voltage to digital output, this methodology can achieve better performance and consume less power.

In order to reduce power consumption, the circuit is extended by the SAR ADC architecture. The circuit architecture can be roughly divided into: sample-and-hold circuit, time-domain comparator, CDAC, SAR control logic and digital ramp charge /discharge and control unit. First, when the circuit is in the sampling stage, the sample and hold circuit will sample the input signal, then circuit entering the conversion stage, the time-domain comparator will convert the sampled input voltage into input time, and compare the speed of the input time to give the corresponding logic signal to CDAC switching and do next compare until the conversion of the first ten bits is completed.

Then, the digital ramp charging/discharging and control unit will perform digital ramp charging/discharging on the input node according to the result of the 10th comparison.
During this period, the time domain comparator compare the difference of input node continuously until the result is different from the result of tenth comparison. At this time, the number of charge/discharge will be recorded and encoded, and finally output 14 bits.

The design is fabricated in a TSMC 0.18μm 1P6M CMOS process with a chip area of 1.163×1.013 mm2 including PADs. The sampling rate of the Time Domain ADC is 20k-S/s, the resolution is 14-bit, and the supply voltages are 1.0V/1.8V. The power consumption is 2uW, the effective number of bits is 12.77 bit and the FOM is 14.3 fJ/c-s by post-simulations.

[1] H. J. Yoo and C. V. Hoof, Bio-Medical CMOS ICs Integrated Circuits and Systems, 2011.
[2] 陳博瑋 , “The Analysis and Design of Successive Approximation Analog-to-Digital Converter for Biomedical Applications,” 長庚大學電子工程研究所碩士論文, Aug. 2004.
[3] A. Agnes, et al. , “A 9.4-ENOB 1V 3.8µW 100kS/s SAR ADC with TimeDomain Comparator,” , IEEE International Solid- State Circuits Conference (ISSCC), Feb. 2008.
[4] S.-K. Lee, S.-J. Park, H.-J. Park, and J.-Y. Sim, “A 21 fj/conversion-step 100 ks/s 10-bit adc with a low-Noise time-domain comparator for lowpower sensor interface,” Solid-State Circuits, IEEE Journal, March 2011.
[5] Walt Kester, Analog-Digital Conversion, Analog Devices, 2004, Chapter 6.
[6] C. Hsieh and S. Liu, “A 0.3v 10bit 7.3fj/conversion-step sar adc in 0.18µm cmos,” IEEE Asian Solid-State Circuits Conference (ASSCC) , Nov 2014.
[7] M. Dessouky and A. Kaiser, “Input switch configuration suitable for rail-to-rail operation of switched op amp circuits,” in Electronics Letters, Jan. 1999..
[8] J. Lin and C. Hsieh, “A 0.3 V 10-bit SAR ADC With First 2-bit Guess in 90-nm CMOS,” IEEE Transactions on Circuits and Systems I, March 2017.74.
[9] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor Switching procedure,” IEEE J. Solid-State Circuits, Apr. 2010.
[10] J. H. Cheong, K. L. Chan, P. B. Khannur, K. T. Tiew, and M. Je, “A 400-nW 19.5-fJ/conversion-step 8-ENOB 80-kS/s SAR ADC in 0.18-μm CMOS” IEEE Trans. Circuits Syst. II, Jul. 2011.

[11] Y.-J. Chen, K.-H. Chang, and C.-C. Hsieh, “A 2.02–5.16 fJ/conversion step 10 bit hybrid coarse-fine SAR ADC with time-domain quantizer in 90 nm CMOS” IEEE J. Solid-State Circuits,Feb. 2016.
[12] S. Naraghi, M. Courcy, and M. P. Flynn, “A 9-bit, 14μW and 0.06mm2 pulse position modulation ADC in 90 nm digital CMOS” IEEE J. Solid-State Circuits, Sep. 2010.
[13] P. J. A. Harpe, C. Zhou, K. Philips, and H. de Groot, “A 0.8-mW 5-bit 250-MS/s time-interleaved asynchronous digital slope ADC” IEEE J. Solid-State Circuits, Nov. 2011.
[14] C. Liu, M. Huang, and Y.-H. Tu, ‘‘A 12 bit 100 MS/s SAR-assisted digitalslope ADC,’’ IEEE J. Solid-State Circuits, Dec. 2016.
[15] Jere A. M. Jarvinen, Mikko Saukoski, and Kari Halonen, “ A 12-Bit Ratio-Independent Algorithmic A/D Converter for a Capacitive Sensor Interface” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I, Apr 2008.
[16] W. Mao, Y. Li, C.-H. Heng, and Y. Lian, “A low power 12-bit 1-kS/s SAR ADC for biomedical signal processing,” IEEE Trans. Circuits Syst. I, Feb. 2019.
[17] Xiaoyan Gui, Marjan Gusev, Nevena Ackovska, Yanlong Zhang and Li Geng, “ A 12-Bit 20-kS/s 640-nW SAR ADC With a VCDL-Based Open-Loop Time-Domain Comparator “ IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II, Feb 2022.
[18] J. Muhlestein, S. Leuenberger, H. Sun, Y. Xu, and U.-K. Moon, “A 73dB SNDR 20MS/s 1.28mW SAR-TDC using hybrid two-step quantization,”, IEEE Custom Integr. Circuits Conf., Sep. 2017
[19] Haoyi Zhao, Fa Foster Dai, “ A 0.97mW 260MS/s 12b Pipelined-SAR ADC with Ring-TDC-Based Fine Quantizer for PVT Robust Automatic Cross-Domain Scale Alignment “ IEEE International Solid- State Circuits Conference (ISSCC),Feb. 2022.
[20] Hsieh S-e, Ho C-k, Hsieh C-c., “A 1.2V 1MS/s 7.65fJ/Conversion-step 12-bit hybrid SAR ADC with time-to-digital converter.”, IEEE International Symposium on Circuits and Systems (ISCAS); May. 2015.
[21] 林韋成, “ A Low Power Low Cost High Resolution Time-Domain Analog-to-Digital Converter with Self-Calibration for Bio-Sensing Applications.”, Jul. 2013.