本論文主要研究在多層電路設計中，因數位IC本身快速切換產生的瞬時電流，進而在另一端的類比IC產生同步切換雜訊(Simultaneous Switching Noise)。此雜訊會在電源輸送網路(Power Delivery Network, PDN)中傳播，使整個系統電路的電源完整性(Power integrity, PI)受到影響。而在本文中，主要的多層印刷電路板（Multi-layer Printed Circuit Board）設計中心理念是透過週期性(Periodic Structure)的交錯式電磁能隙 (Interleaved EBG)結構，並改變此結構的板材厚度，來達到阻抗不連續的特性，增加其隔離度。接著嵌入槽線(Slot Line)，使其架構產生多模態的激發，藉此得到寬頻抑制的效果。從頻域上觀察，此架構在5×5的週期性結構中頻寬範圍從0.56 GHz至20 GHz皆抑制於-40 dB以下，僅7.24 GHz此單一頻率點特性較差。另外，因為週期性結構的特性，使其在任意位置都有良好的隔離效果。

This thesis mainly studies the instantaneous current is generated by the high clock switching of the digital device in the multilayer printed circuit board, and then brings the simultaneous switching noise (SSN) in the analog device or sensitivity device. The SSN propagates through the power delivery network (PDN) which affects the power integrity (PI) of the system circuit. In this research, the main idea of the circuit design is the periodic structure of interleaved EBG structure. Then change the thickness of the structure to achieve the impedance discontinuity and increase its isolation. Next, the slot line is embedded in the inner layer to create the multi-mode excitation. Thereby getting the broadband suppression. From the frequency domain observation, the bandwidth of this architecture can efficiently suppress the SSN below -40 dB from 0.56 GHz to 20 GHz in the 5×5 periodic structure, and only a single frequency point characteristic of the 7.24 GHz is relatively poor. In addition, due to the characteristics of the periodic structure, it has a good isolation effect at any position.

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