現代的無線通訊系統，其中之頻率合成器的功能是處理訊號頻率的升降頻。於頻率合成器電路中，電壓控制振盪器與除頻器是很重要的核心電路。就電壓控制振盪器而言，其設計必須提供低相位雜訊的輸出，進而避免相鄰雜訊經由混波轉換過程中發生不利的干擾。頻率合成器電路中，振盪器的輸出訊號乃經由除頻器來達成降頻的工作，為了達到這個目的，除頻器的設計方向往往是具有高頻操作、寬廣的操作頻寬及低功率消耗性能表現來實現。

採用單注入式雙注入MOSFET之新型除四注入鎖定除頻器晶片的設計，以台積電製程 0.18 μm BiCMOS實現。電路供應電壓為0.8V，採用之壓控振盪器並連LC響應的可調電路，操作頻率範圍從15.85GHz至19.08 GHz，為18.49%，達3.23 GHz。電路核心電流8.16mA，功率消耗為6.53mW，divide-by-4 ILFD晶片面積為0.83* 0.597 mm2。

此論文中又以過電壓應力實驗的方式來進行評估熱載子效應。加壓電壓為2.0 V，其時間為50分鐘，評估對上述RF的台積電零點一八微米製程電路的除四注入鎖定除頻器(ILFD)特性的影響。量測結果顯示高頻帶與低頻帶的鎖定範圍，會隨著加壓的時間增加影響而減少操作範圍，導致電路失去原有之性能來做研究。

最後一個過電壓應力實驗，用在一個雙共振模式之注入鎖定除頻率器，研究應力後的射頻性能。注入鎖定除頻率器是以台積電 0.18 μ m 1P6M CMOS 製程實現，它是以電壓 2.3V加壓，其間共5個小時用以進行評估熱載子效應。加壓應力減少了高頻率和低頻率波段兩個的鎖定範圍，隨著應力時間的增加，降低其振盪器自由振盪頻率的相位雜訊，和注入鎖定狀態的性能降低。而熱載子效應會改變振盪器的頻率、功率消耗還有相位雜訊。

Modern wireless communication systems, which feature of frequency synthesizer is to handle the lifting or descending the frequency of the signals. For practice in frequency synthesizer circuit, voltage-controlled oscillator (VCO) in core circuit of system that plays a key role. Voltage-controlled oscillator, its design must provide low phase noise output to avoid degrading the mixer-converted signal by adjacent through reverberation noise and cross-interfering tunes. Oscillator output signal comes through in addition to injection-locked frequency divider (ILFD) for lower frequency band. In order to achieve these designs, the key factors of operation performance with a high frequency operation, broad bandwidth and low power consumption to achieve.

A wide locking range and operation range push-push divide-by-4 injection-locked frequency divider is proposed in the letter and was implemented in the TSMC 0.18 μm 3P6M BiCMOS process. The divide-by-4 ILFD uses a cross-coupled voltage-controlled oscillator (VCO) with a parallel-tuned LC resonator for easy startup oscillation and dual injection transistors. At the drain-source bias of 0.8 V, and at the incident power of 0 dBm the operation range of the divide-by-4 is 3.23 GHz, from the incident frequency 15.85 to 19.08 GHz, the percentage is 18.49%. The core power consumption is 6.53mW. The die area is 0.83×0.597 mm2.

This paper experimentally investigates the hot carrier effects on the RF characteristics of a divide-by-4 injection-locked frequency divider (ILFD). It was implemented in the TSMC 0.18 μm CMOS process as mentioned chip above. High supply voltage was applied to excite high RF voltage stress on the ILFD. ILFDcore-current and power consumptions decrease with stress time. This locking range degradation is caused by the transconductance degradation of injection MOSFETs and low ILFD voltage swing.

Lastly, over-voltage stress was applied to a dual-resonance injection-locked frequency divider (ILFD) to study the post-stress RF performance. The ILFD was implemented in the TSMC 0.18 μm 1P6M CMOS process and it was stressed at the supply voltage of 2.3V for 5 hours. The stress reduces both the high-frequency and low-frequency band locking ranges. The phase noises in the free-running and locked state decrease with stress time.

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