本論文描述應用於短距離無線通訊之射頻收發機前端電路的晶片設計，並以CMOS 0.18 μm製程設計兩個射頻前端電路晶片，由於電池壽命對於移動式無線通訊和低功率操作是至關重要的，而電池壽命是受限於電子電路的功率消秏，為了能減少所需的功率消秏，降低電路的操作電壓顯然是個有效的方法，所以本論文提出的兩個射頻前端電路均設計在低電壓的操作下。
第一個晶片是接收機電路，在接收機電路中整合電流再利用架構的低雜訊放大器、折疊架構的Gilbert cell混波器、Colpitts架構的壓控振盪器以及Gm-C架構的中頻帶通濾波器。另一個晶片是射頻收發機前端電路，在射頻收發機前端電路中整合非對稱架構的收發切換器、電流再利用架構的低雜訊放大器以及Class A功率放大器。
在接收機電路的量測結果中，量測到的S11為-20 dB、CG為29 dB、(DSB) NF before filtering為5 dB、與IIP3為-24.4 dBm。而內建於接收機電路中的振盪器所量測到的tuning range為5.17 GHz到5.98 GHz、在操作頻率5.8 GHz位移1 MHz下的phase noise為-118.5 dBc/Hz，該晶片包含PADs在內的面積為1.75 x 1.2 mm2，在接收機前端電路的操作電壓為1 V下的接收機功率消秏為27.6 mW。在收發機前端電路的量測結果中，接收模式下所量測到的power gain為11dB、NF為4.9 dB、與IIP3為-5.4 dBm，傳送模式下所量測到的power gain為12.4 dB、OP-1dB為11.4 dBm、與在P-1dB處的PAE為14.7 %，該晶片包含PADs在內的面積為1.32 x 1.14 mm2，在操作電壓1 V下的低雜訊放大器電流消秏為3.9 mA，在操作電壓1.8 V下的功率放大器電流消秏為64.6 mA，而在操作電壓1.8 V下的收發切換器電流消秏為0 mA。

The thesis describes the RF transceiver front-end chip design for DSRC (Dedicated Short Range Communications) applications, and two RF front-end chips are designed by the CMOS 0.18 μm process. For mobile wireless communications and low power operations are crucial to the battery lifetime limited by the power consumption of the electronic circuits. In order to minimize the required power consumption, operating the circuits at the low supply voltage is apparently an effective approach, so the two proposed RF front-end chips of the thesis are designed on the low voltage operation.
The first proposed chip is the RF receiver, including a current-reused LNA, a folded Gilbert cell mixer, a Colpitts VCO, and an IF Gm-C bandpass filter. The other proposed chip is the RF transceiver front-end, including an asymmetrical T/R switch, a current-reused LNA, and a Class A PA.
The measured results of the receiver show the input return loss of 20 dB, the conversion gain of 29 dB, the (DSB) NF of 5 dB, and the third-order intercept point (IIP3) of -24.4 dBm. The local oscillator built in the receiver shows the measured tuning range of 5.17 GHz to 5.98 GHz and the phase noise of -118.5 dBc/Hz at 1 MHz offset from a 5.8 GHz carrier. The overall chip area including pads is 1.75 x 1.2 mm2 with the receiver power consumption of 27.6 mW under the receiver front-end supply voltage of 1 V. The measured results of the transceiver front-end show the power gain of 11 dB, the NF of 4.9 dB, and the third-order intercept point (IIP3) of -5.4 dBm in the Rx mode. On the other hand, the measured results of the transceiver front-end show the power gain of 12.4 dB, the output 1 dB compression point (OP-1dB) of 11.4 dBm, and the PAE of 14.7% at P-1dB is obtained in the Tx mode. The overall chip area including pads is 1.32 x 1.14 mm2 with the LNA current consumption of 3.9 mA under the supply voltage of 1 V, the PA current consumption of 64.6 mA under the supply voltage of 1.8 V, and the T/R switch current consumption of 0 mA under the supply voltage of 1.8 V.

[1] T.H. LEE, The Design of CMOS Radio-Freq. Integrated Circuits, 2nd ed., Cambridge, 2004, pp. 136-148.
[2] N. Sasho, K. Minami, H. Fujita, T. Takahashi, K. Iimura, M. Abe, and A. Yasuda, “Single-chip 5.8 GHz DSRC transceiver with dual-mode of ASK and Pi/4-QPSK,” in Proc. IEEE Radio Wireless Symp., pp. 799–802, Jan. 2008.
[3] S. Shin, S. Yun, S. Cho, J. Kim, M. Kang, W. Oh, S.-M. Kang, “0.18um CMOS Integrated Chipset for 5.8GHz DSRC Systems with +10dBm Output Power,” in Proc. IEEE Symp. on Circuits and Systems, pp. 1958-1961, May 2008.
[4] K. Kwon, J. Choi, J. Choi, Y. Hwang, K. Lee, and J. Ko, “A 5.8 GHz Integrated CMOS Dedicated Short Range Communication Transceiver for the Korea/Japan Electronic Toll Collection System,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 11, pp. 2751-2763, Nov. 2010.
[5] H.T. Friis, “Noise Figures of Radio Receivers,” in Proc. IRE, vol. 32, no. 7, pp. 419–422, Jul. 1944.
[6] D. Ham and A. Hajimiri, “Concepts and methods in optimization of integrated LC VCOs,” IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 896-909, Jun. 2001.
[7] M.J. Deen, B. Iniguez, O. Marinov, and F. Lime, “Electrical Studies of Semiconductor-Dielectric Interfaces,” J. Materials Science: Materials in Electronics, vol. 17, no. 9, pp. 663-683, Sep. 2006.
[8] R. Aparicio and A. Hajimiri “A noise-shifting differential Colpitts VCO,” IEEE J. Solid-State Circuits, vol. 37, no. 12, Dec. 2002.
[9] B. Nauta "A CMOS Transconductance-C Filter Technique for Very High Frequencies". IEEE J. Solid State Circuits, vol. 27, no. 2, pp. 142-153, Feb. 1992.
[10] M.A. Abdelghany, A.I.A. Galal, R.K. Pokharel, and K. Yoshida, “A Low Flicker Noise Direct Conversion Receiver for the IEEE 802.11a Wireless LAN Standard,” in Proc. Asia Pacific Microw. Conf., pp. 1647-1650, Dec. 2009.
[11] J.-T. Yang, D.-W. Shen, P.-J. Tsai, and M.-J. Wu, “A CMOS Radio Frequency Receiver for Bluetooth Applications,” in Proc. 1st Asia Quality Electronic Design Symp., pp. 352-356, Jul. 2009.
[12] W. Chen, T. Copani, H.J. Barnaby, and S. Kiae, “A 14-GHz CMOS Receiver with Local Oscillator and IF Bandpass Filter for Satellite Applications,” in Proc. IEEE Radio Freq. Integrated Circuits Symp., pp. 123-126, Jun. 2009.
[13] J.-H. Wang, H.-H. Hsieh, and L.-H. Lu, "A 5.2-GHz CMOS T/R Switch for Ultra-low-Voltage Operations," IEEE Trans. Microw. Theory Tech., vol. 56, no. 8, pp. 1774-1782, Aug. 2008.
[14] N.A. Talwalkar, C.P. Yue, H. Gan, and S.S. Wong, "Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications," IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 863-870, Jun. 2004.
[15] A.A. Kidwai, C.T. Fu, J.C. Jensen, and S.S. Taylor, "A fully Integrated Ultra-Low Insertion Loss T/R Switch for 802.11b/g/n Application in 90 nm CMOS Process," IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1352-1360, May 2009.
[16] P. Piljae, S.D. Hun, and C.P. Yue, "High-Linearity CMOS T/R Switch Design Above 20 GHz Using Asymmetrical Topology and AC-Floating Bias," IEEE Trans. Microw. Theory Tech., vol. 57, no. 4, pp. 948-956, Apr. 2009.
[17] H. Kanaya, F. Koga, K. Seki, and K. Yoshida, ”Impedance Matching Circuit for Wireless Transceiver Amplifier Based on Transmission Line Theory,” in Proc. Asia Pacific Microw. Conf., vol. 5, Dec. 2005.
[18] C.-F. Jou, P.-R. Huang, and K.-H. Cheng, “DESIGN OF A 0.25-pm CMOS 5.25GHZ TRANSCEIVER FRONT-END,” in Proc. IEEE Int. Conf. on Electronics, Circuits and systems, vol. 3, Dec. 2003.
[19] K. Yamamoto, T. Heima, A. Furukawa, M. Ono, Y. Hashizume, H. Komurasaki, S. Maeda, H. Sato, and N. Kato, “A 2.4-GHz-Band 1.8-V Operation Single-Chip Si-CMOS T/R-MMIC Front-End with a Low Insertion Loss Switch,” IEEE J. Solid-State Circuits, vol. 36, no. 8, Aug. 2001.