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研究生： 許庭瀚
Ting-Han Hsu
論文名稱： 高速、高解析度及低功耗之逐漸逼近式類比數位轉換器積體電路設計與驗證
Integrated Circuit Design and Verification of Successive Approximation Register Analog-to-Digital Converters for High Speed, High Resolution, and Low Power Applications
指導教授： 彭盛裕
Sheng-Yu Peng
口試委員: 姚嘉瑜
Chia-Yu Yao
陳筱青
Hsiao-Chin Chen
學位類別： 碩士
Master
系所名稱： 電資學院 - 電機工程系
Department of Electrical Engineering
論文出版年： 2022
畢業學年度： 110
語文別： 英文
論文頁數： 112
中文關鍵詞： 高速 、高解析度 、低功耗 、類比數位轉換器 、數位類比轉換器 、逐漸逼近式 、逐漸逼近式類比數位轉換器 、積體電路 、高速、高解析度及低功耗之逐漸逼近式類比數位轉換器積體電路設計與驗證
外文關鍵詞： Integrated Circuit Design, Analog-to-Digital Converters, Digital-to-Analog Converters, Integrated Circuit Design and Verification of Successive Approximation Register Analog-to-Digital Converters for High Speed, High Resolution, and Low Power Applications
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    • Abstract in Chinese . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Abstract in English . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Background Knowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Fundamental SAR ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Fully Differential SAR ADCs . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.1 Split Capacitor Array SAR ADC . . . . . . . . . . . . . . . . . . . . . 11 2.2.2 Monotonic Switching SAR ADC . . . . . . . . . . . . . . . . . . . . . . 13 2.2.3 Switchback Switching SAR ADC . . . . . . . . . . . . . . . . . . . . . . 15 2.2.4 Vcm-Based Switching SAR ADC . . . . . . . . . . . . . . . . . . . . . . 17 2.2.5 CAP and DAC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3 High Speed ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.1 Redundancy Technique . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.2 Reference Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.3 Clock Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3.4 ADC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3 The SAR ADC in 180 nm Implementation . . . . . . . . . . . . . . . . . . . . . . 28 3.1 9Bit36MS/s SAR ADC with Direct Switching and Redundancy Techniques . . . . . 28 3.1.1 SAR ADC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.1.2 Sample-and-Hold Switch Design . . . . . . . . . . . . . . . . . . . . . 30 3.1.3 Dynamic Comparator Design . . . . . . . . . . . . . . . . . . . . . . . 34 3.1.4 Noise Arrangement and Analysis . . . . . . . . . . . . . . . . . . . . . 39 3.1.5 SAR Control Logic and Digital Error Correction . . . . . . . . . . . . . 41 3.1.6 Direct Switching Logics Design . . . . . . . . . . . . . . . . . . . . . 43 3.1.7 Capacitive Array DAC Design . . . . . . . . . . . . . . . . . . . . . . .47 3.1.8 Reference Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.1.9 9-b SAR ADC Simulation Results . . . . . . . . . . . . . . . . . . . . . 53 3.1.10 Layout and Measurement Results . . . . . . . . . . . . . . . . . . . . 54 3.2 12Bit-1MS/s SAR ADC with Redundancy Technique . . . . . . . . . . . . . . . 60 3.2.1 SAR ADC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.2.2 Sample-and-Hold Switch Design . . . . . . . . . . . . . . . . . . . . . 62 3.2.3 Dynamic Comparator Design . . . . . . . . . . . . . . . . . . . . . . . 64 3.2.4 Capacitive Array DAC Design . . . . . . . . . . . . . . . . . . . . . . 65 3.2.5 12b-SAR ADC Simulation Results . . . . . . . . . . . . . . . . . . . . . 67 3.2.6 Layout and Measurement Results . . . . . . . . . . . . . . . . . . . . . 68 3.2.7 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4 The Low Power SAR ADC in 350nm Implementation . . . . . . . . . . . . . . . . . 75 4.1 10-Bit-200KS/s Signal Range Conversion SAR ADC . . . . . . . . . . . . . . . 76 4.1.1 SAR ADC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.1.2 Capacitive Input Attenuation Circuit Design . . . . . . . . . . . . . . 77 4.1.3 Capacitive Array DAC Design . . . . . . . . . . . . . . . . . . . . . . 82 4.1.4 Layout and Measurement Results . . . . . . . . . . . . . . . . . . . . . 83 5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Letter of Authority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

    [1] C.C. Liu and et al., “A 10bit 100MS/ s 1.13mW SAR ADC with binaryscaled error compensation,” IEEE International SolidState Circuits Conference, 2010.
    [2] C.H. Chan and et al., “60dB SNDR 100–MS/s SAR ADCs with threshold reconfigurable reference error calibration,” JSSC, vol. 52, pp. 2576–2588, 2017.
    [3] C. AzeredoLeme, “Clock jitter effects on sampling: A tutorial,” IEEE Circuits and Systems Magazine, vol. 11, no. 3, pp. 26–37, 2011.
    [4] C.P. Huang and et al., “Analysis of nonideal behaviors based on INL/DNL plots for SAR ADCs,” Transactions on Instrumentation and Measurement, vol. 65, no. 8, pp. 1804–1817, 2016.
    [5] W.C. Luo, S.J. Chang, C.P. Huang, and H.S. Wu, “A 11bit 35MS/ s wide input range SAR ADC in 180nm CMOS process,” IEEE International Symposium on VLSI Design, Automation and Test, Automation and Test (VLSIDAT), pp. 1–14, 2018.
    [6] T.Y. Wang, H.Y. Li, Z.Y. Ma, Y.J. Huang, and S.Y. Peng, “A bypassswitching SAR ADC with a dynamic proximity comparator for biomedical applications,” IEEE Journal of Solid–State Circuits, vol. 53, no. 6, pp. 1743–1754, 2018.
    [7] G.Y. Huang, S.J. Chang, C.C. Liu, and Y.Z. Lin, “A 1uW 10bit 200kS/ s SAR ADC with a bypass window for biomedical applications,” IEEE Journal of Solid– State Circuits, vol. 47, no. 11, pp. 2783–2795, 2012.
    [8] J. Guerber, H. Venkatram, M. Gande, A. Waters, and U.K. Moon, “A 10b ternary SAR ADC with quantization time information utilization,” IEEE Journal of Solid– State Circuits, vol. 47, no. 11, pp. 2604 – 2613, 2012.
    [9] F. M. Yaul and A. P. Chandrakasan, “A 10 bit SAR ADC with datadependent energy reduction using LSBfirst successive approximation,” IEEE Journal of Solid–State Circuits, vol. 49, no. 12, pp. 2825–2834, 2014.
    [10] D. Zhang, A. Bhide, and A. Alvandpour, “A 53nW 9.1ENOB 1kS/ s SAR ADC in 0.13um CMOS for medical implant devices,” IEEE Journal of Solid–State Circuits, vol. 47, no. 7, pp. 1585–1593, 2011.
    [11] D. Gangopadhyay, E. G. Allstot, A. M. R. Dixon, K. Natarajan, S. Gupta, and D. J. Allstot, “Compressed sensing analog frontend for biosensor applications,” IEEE Journal of Solid–State Circuits, vol. 49, no. 2, pp. 426–438, 2014.
    [12] M. V. Elzakker, E. v. Tuijl, P. Geraedts, D. Schinkel, E. A. M. Klumperink, and B. Nauta, “A 10bit chargeredistribution ADC consuming 1.9 uW at 1 MS/s,” IEEE Journal of Solid–State Circuits, vol. 45, no. 5, pp. 1007–1015, 2010.
    [13] C.C. Liu, S.J. Chang, G.Y. Huang, and Y.Z. Lin, “A 10bit 50MS/ s SAR ADC with a monotonic capacitor switching procedure,” IEEE Journal of Solid–State Circuits, vol. 45, no. 4, pp. 731–740, 2010.
    [14] H.Y. Tai, Y.S. Hu, H.W. Chen, and H.S. Chen, “A 0.85fJ/conversionstep 10b 200ks/s subranging SAR ADC in 40nm CMOS,” IEEE International SolidState Circuits Conference, pp. 196–198, 2014.
    [15] Z. Zhu and Y. Liang, “A 0.6V 38nW 9.4ENOB 20kS/ s SAR ADC in 0.18um CMOS for medical implant devices,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 62, no. 9, pp. 2167–2176, 2015.
    [16] S. Liu, Y. Shen, and Z. Zhu, “A 12bit 10 MS/s SAR ADC with high linearity and energyefficient switching,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 63, no. 10, pp. 1616–1627, 2016.
    [17] P. Harpe, E. Cantatore, and A. v. Roermund, “A 10b/12b 40 kS/s SAR ADC with datadriven noise reduction achieving up to 10.1b ENOB at 2.2 fJ/conversionstep,” IEEE Journal of Solid–State Circuits, vol. 48, no. 12, pp. 3001–3018, 2013.
    [18] M. Ahmadi and W. Namgoong, “Comparator power minimization analysis for SAR ADC using multiple comparators,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 62, no. 10, pp. 2369–2379, 2015.
    [19] A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “A 0.5 V 1.1 MS/sec 6.3 fJ/ conversionstep SARADC with trilevel comparator in 40 nm CMOS,” IEEE Journal of Solid–State Circuits, vol. 47, no. 4, pp. 1022–1030, 2012.
    [20] J. Sauerbrey, D. SchmittLandsiedel, and R. Thewes, “A 0.5V 1μw successive approximation ADC,” Proceedings of the Symposium on VLSI Circuits, pp. 236– 237, 2009.
    [21] S.H. Wan, C.H. Kuo, S.J. Chang;, G.Y. f, C.P. Huang, G.J. Ren, K.T. Chiou, and C.H. Ho, “A 10bit 50MS/ s SAR ADC with techniques for relaxing the requirement on driving capability of reference voltage buffers,” IEEE Asian SolidState Circuits Conference, pp. 293–296, 2013.
    [22] B. P. Ginsburg and A. P. Chandrakasan, “500MS/ s 5bit ADC in 65nm CMOS with split capacitor array DAC,” IEEE Journal of Solid–State Circuits, vol. 42, no. 4, pp. 739–747, 2007.
    [23] G.Y. Huang, C.C. Liu, C.C. Liu, and Y.Z. Lin, “10bit 30MS/ s SAR ADC using a switchback switching method,” IEEE Transactions on Very Large Scale Integration Systems, vol. 21, no. 3, pp. 584–588, 2013.
    [24] V. Hariprasath, J. Guerber, S. H. Lee, and U. Moon, “Merged capacitor switching based SAR ADC with highest switching energy efficiency,” IEEE Electronics Letters, vol. 46, no. 9, pp. 620–621, 2010.
    [25] F. Kuttner, “A 1.2V 10bit 20MSample/ s nonbinary successive approximation ADC in 0.13μm CMOS,” IEEE International SolidState Circuits Conference, 2002.
    [26] S.W. M. Chen and R. W. Brodersen, “A 6bit 600MS/ s 5.3mW asynchronous ADC in 0.13um CMOS,” IEEE Journal of Solid–State Circuits, vol. 41, pp. 2269–2680, 2006.
    [27] M. Liu, A. H. M. van Roermund, and P. Harpe, “A 10b 20MS/ s SAR ADC with DACcompensated discretetime reference driver,” IEEE Journal of Solid–State Circuits, vol. 54, no. 2, pp. 417–427, 2019.
    [28] G.Y. Huang, S.J. Chang, Y.Z. Lin, C.C. Liu, and C.P. Huang, “A 10b 200MS/s 0.82mw SAR ADC in 40nm CMOS,” IEEE Asian SolidState Circuits Conference, pp. 289–292, 2013.
    [29] B. Razavi, “The bootstrapped switch,” IEEE SolidState Circuits Magazine, vol. 7, no. 3, pp. 12–15, 2015.
    [30] B. Razavi, “The StrongARM latch,” IEEE SolidState Circuits Magazine, vol. 7, no. 2, pp. 12–17, 2015.
    [31] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. A. M. Klumperink, and B. Nauta, “A 10bit chargeredistribution ADC consuming 1.9 μw at 1 MS/s,” IEEE Journal of Solid–State Circuits, vol. 45, no. 5, pp. 1007–1015, 2010.
    [32] W.H. Tsai, C.H. Kuo, S.J. Chang, L.T. Lo, Y.C. Wu, and C.J. Chen, “A 10bit 50MS/ s SAR ADC for dualvoltage domain portable systems,” IEEE Proceedings of the International Symposium on Circuits and Systems, pp. 2425–2428, 2015.
    [33] S. Chaput, D. Brooks, and G.Y. Wei, “An areaefficient 8bit singleended ADC with extended input voltage range,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 65, no. 11, pp. 1549–1553, 2018.

    無法下載圖示 全文公開日期 2027/01/19 (校內網路)
    全文公開日期 2027/01/19 (校外網路)
    全文公開日期 2027/01/19 (國家圖書館：臺灣博碩士論文系統)
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