在射頻收發機裡，PLL的特性非常重要，PLL內包含了頻率相位偵測器、充電幫浦、迴路濾波器、壓控振盪器、除頻器、倍頻器，低功耗，低相位雜訊，較寬的工作頻率範圍，是除頻器和倍頻器的特性。
本論文分為三個部分。第一部分，研究注入鎖定震盪器的射頻特性來做倍頻器，第二部分，研究BiCMOS注入鎖定倍頻器，BiCMOS是種新半導體技術，將雙極性電晶體和互補式金屬氧化物半導體集成到積體電路上，第三部分，研究利用除四注入鎖定除頻器混波，模擬除五注入鎖定除頻器。
首先，我們呈現兩個注入鎖定除頻器和倍頻器，使用了台積電0.18微米製程，兩個注入場效電晶體的交叉耦合注入鎖定振盪器，單頻振盪器在直流偏壓為0.8V時，模擬在注入能量0dBm時的倍頻1.5倍範圍為2.7~3.0 GHz (10.5%)，晶片面積為0.659×0.887 mm2。雙頻振盪器有兩個不重疊的鎖定頻帶，倍頻範圍為1.24~1.7 GHz 和2.86~3.5 GHz，晶片面積為0.996×0.868 mm2。
再來第二個電路，我們呈現BiCMOS注入鎖定倍頻器，此倍頻器使用台積電0.18微米製程，功耗為8.56 mW調節可調式電容偏壓，頻率範圍為3.4~3.853 GHz，注入鎖定倍頻3倍範圍為1.03~1.32 GHz (24.68%)，晶片面積為0.62×0.951 mm2。
最後第三個電路，探討一個使用台積電0.18微米製程之電容交叉耦合除五注入鎖定除頻器，藉由調整MOSFET之閘極開關來取得最佳的除頻範圍，輸入四倍頻的訊號會在輸出端產生一個五倍頻的訊號，已達到混波效果，當工作電壓操作在0.8伏特，注入訊號強度為 0 dBm時，模擬得注入鎖定頻帶為11.5 ~ 13.3 GHz，除頻比例為14.5%，晶片面積為0.715 × 0.831 mm2。

In the RF transceiver, PLL characteristics are very important, PLL includes Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF), Voltage Controlled Oscillator (VCO), Frequency Divider (FD), and Frequency Multiplier (FM), among them, the most important circuits are the VCO, Divider, and Multiplier.
This thesis has three parts. The first part is to study the RF property of injection-locked oscillators (ILOs) used as frequency multiplier (FM). The second part is to study BiCMOS injection-locked frequency multiplier (ILFM). BiCMOS is a new semiconductor technology that integrates bipolar junction transistor (BJT) and Complementary Metal-Oxide-Semiconductor (CMOS) on the integrated circuit. The third part is to study the ILFD combining one divide-by-5 ILFD with one embedded divide-by-4 ILFD, the divide-by-5 ILFD generates a 4th harmonic used as the input of the divide-by-4 ILFD.
First, we present injection-locked frequency divider (ILFD) and frequency multiplier (ILFM) using a standard TSMC 0.18 μm 1P6M CMOS process. The ILOs are realized with a cross-coupled ILO with two injection FETs in shunt with the single-resonance resonator and dual-resonance resonator. The core power consumption of the single-resonance resonator is at the dc drain-source bias of 0.8 V. At the input power of 0 dBm, the multiply-by-1.5 ILFM simulates the locking range from 2.7 GHz to 3.0 GHz (10.5 %), and the die area is 0.659 × 0.887 mm2. Dual-resonance resonator ILFD has dual-band locking ranges. The ×1.5 ILFM simulates the locking range from 1.24 to 1.7 GHz and from 2.86 to 3.5 GHz, by a silicon chip area of 0.996 × 0.868 mm2.
Secondly, we present a BiCMOS injection-locked frequency multiplier. This frequency multiplier (FM) uses a standard TSMC 0.18 μm 1P6M CMOS process, and consumes the power of 8.56 mW. The oscillation frequency range is from 3.4 to 3.853 GHz. The input multiplier-by-3 operation range is from 1.03 to 1.32 GHz, and the chip area is 0.62×0.951 mm2.
Finally, the last circuit is to explore a capacitive cross-coupled divider divided by five injection-locked frequency divide on using a standard TSMC 0.18 μm 1P6M CMOS process.
This ILFD combines one divide-by-5 ILFD with one embedded divide-by-4 ILFD, the divide-by-5 ILFD generates a 4th harmonic used as the input of the divide-by-4 ILFD. At the incident power of 0 dBm, the simulated locking range of the divide-by-5 ILFD is 1.8 GHz, from the incident frequency 11.5 GHz to 13.3 GHz, the percentage is 14.5%. Tuning the gate bias of injection FET in the divide-by-4 ILFD extends the operation range. The die area is 0.715 ×0.831 mm2.

[1] B. Razavi, “RF Microelectronics”, Upper Saddle River, NJ: Prentice Hall, 1998
[2] N. M.Nguyen and R. G. Meyer, “Start-up and frequency stability in high-frequency oscillators,” IEEE J. Solid-State Circuit, vol. 27, no. 5, pp. 810–820, May 1992.
[3] B. Razavi, “Design of Analog CMOS Integrated Circuit”,Mc Graw Hill,2008.
[4] J. Roggers, C. Plett, Radio frequency integrated circuit design, Artech House, 2003.
[5] B. Razavi , Design of Integrated Circuits for Optical Communications”, Mc Graw Hill.
[6] B. Razavi, “Design of Analog CMOS Integrated Circuits”, Mc Graw Hill, 2001.
[7] J. van der Tang, and D. Kasperkovitz, “Oscillator design efficiency: a new figure of merit for oscillator benchmarking,” IEEE International Symposium on Circuit and System (ISCAS), vol. 2, pp. 533-536, May 2000.
[8] J.J. Rael, and A. A. Abidi, “Physical processes of phase noise in differential LC oscillators,” IEEE Custom Integrated Circuits Conference, pp. 569–572, 2000.
[9] T. Lee and A. Hajimiri, “Oscillator phase noise: a tutorial,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 326–336, Mar. 2000.
[10] D. Leeson, “A simple model of feedback oscillator noise spectrum,” Proceedings of the IEEE, vol. 54, pp. 329–330, Feb. 1966.
[11] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179–194, Feb. 1998.
[12] T. H. Lee and A. Hajimiri, “Oscillator phase noise: a tutorial,” IEEE J. Solid-State Circuit, vol. 35, no. 3, pp. 326–336, Mar. 2000.
[13] T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge University Press 1998.
[14] H. M. Greenhouse, “Design of planar rectangular microelectronic inductors,” IEEE Transactions on Parts, Hybrids, and Packaging, vol. 10, pp. 101-109, Jun 1974.
[15] J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE J. Solid-State Circuits, vol. 35, pp. 1368-1382, Sept. 2000.
[16] A . Zolfaghari, A. Chan, and B. Razavi, “Stacked inductors and transformers in CMOS technology,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 620-628, Apr. 2001.
[17] P. Andreani, S. Mattisson, “On the use of MOS varactors in RF VCOs,” IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp. 905-910, June 2000.
[18] J. Craninckx and M. S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/ 129 prescaler in 0.7 um CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 890-897, July 1996.
[19] Q. Huang and R. Rogenmoser, “Speed optimization of edge-triggered CMOS
circuits for gigahertz single-phase clocks,” IEEE J. Solid-State Circuits, vol. 31, pp. 456-463, Mar. 1996.
[20] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18-um CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, pp. 594-601, Apr. 2004.
[21] H. R. Rategh, and T.H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, pp. 813-821, June 1999.
[22] H. D. Wohlmuth and D. Kehrer, “A high sensitivity static 2:1 frequency divider up to 27 GHz in 120 nm CMOS,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 823-826, Sept. 2002.
[23] M. Tiebout, “A 480 uW 2 GHz ultra low power dual-modulus prescaler in 0.25 um standard CMOS,” IEEE International Symposium on Circuit and System (ISCAS), vol. 5, pp. 741-744, May 2000.
[24] H. Wu, and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 μm CMOS frequency divider with shunt-peaking locking-range enhancement,” IEEE ISSCC Dig. Tech. Papers, pp. 412-413, Feb. 2001.
[25] R. J. Betancourt-Zamora, S. Verma, and T. H. Lee, “1 GHz and 2.8 GHz CMOS injection- locked ring oscillator prescalers,” IEEE Symposium on VLSI Circuits, pp. 47-50, June 2001.
[26] P. Kinget, R. Melville, D. Long, and V. Gopinathan, “An Injection Locking
Scheme for Precision Quadrature Generation,” IEEE J. Solid-State Circuits, vol. 37, pp. 845-851, July 2002.
[27] W. Z. Chen, and C. L. Kuo, “18 GHz and 7 GHz superharmonic injection-locked dividers in 0.25pm CMOS technology,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 89-92, Sept. 2002.
[28] H. Wu, “Signal generation and processing in high-frequency/high-speed
silicon-based integrated circuits,” PhD thesis, California Institute of Technology, 2003.
[29] S.-L. Jang, W.-C. Lai, G.-Y. Lin, and C. Y. Huang, “Injection-locked frequency divider with a resistively distributed resonator for wide-lockingrange performance,” IEEE Trans. Microw. Theory Techn., vol. 67, no. 2, pp. 505–517, Feb. 2019.
[30] S. Jang, W. Lai, G. Li and Y. Chen “High even-modulus injection-locked frequency dividers,” IEEE Trans. on Microw. Theory and Tech., vol. 67, no. 12, pp. 5069-5079, Dec. 2019.
[31] W.-C. Lai, J.-W. Jhuang, S.-L. Jang, G.-Y. Lin, and C.-W. Hsue,“Wide-band injection-locked frequency doubler,” IEEE APCCAS, pp. 265 – 268, 2016.
[32] S.-L. Jang, J.-J. Chen, C.-C. Liu and M.-H. Juang, ” Injection-locked frequency tripler with series-tuned resonator in 0.13 μm CMOS technology,” Microw. Optical Tech. Lett., pp.1107-1110, May, 2010.
[33] C.-W. Chang and S.-L. Jang, ”An injection-locked frequency quadrupler in 90 nm CMOS technology,” Microw. Optical Tech. Lett.,55, 2,pp.266-269, Feb. 2013.
[34] P. H. Feng and S. I. Liu, “A current-reused injection-locked frequency multiplication/division circuit in 40 nm CMOS,” IEEE Trans. Microw. Theory Tech., vol. 61, no. 4, pp. 1523–1532, Apr. 2013.
[35] S. Shin, D. R. Utomo, H. Jung, S. Han, J. Kim and S. Lee, "Wide locking-range frequency multiplier by 1.5 employing quadrature injection-locked frequency tripler with embedded notch filtering," IEEE Trans. Microw. Theory Techn., vol. 67, no. 12, pp. 4791-4802, Dec. 2019.
[36] S.-L. Jang, and Jen-Hsiang Hsieh, ” A wide-locking range ÷3 injection-Locked frequency divider using concurrent injection mechanisms,” Analog Integr Circ Sig Process., vol. 77, Issue 3, pp 593-598, Dec. 2013.
[37] S.-L. Jang, Zhi-Hong Wu, Ching-Wen Hsue and Heng-Fa Teng,” Wide-locking range dual-band njection-locked frequency divider,” Microw. Opt. Technol. Lett. vol.55, 10, pp. 2333–2337, October 2013.
[38] J. Zhang, H. Liu, Y. Wu, C. Zhao and K. Kang, " An injection-current-boosting locking-range enhancement technique for ultra-wideband mm-wave injectionlocked frequency triplers," i IEEE Trans. Microw. Theory Techn., vol. 67, no. 7, pp. 3174-3186, July 2019,
[39] Yupeng Fu, Lianming Li, Dongming Wang, Xuan Wang, Xu Wu, "A 31.5-to-40.5 GHz injection-locked CMOS frequency tripler with injection-current enhancement technique", IEICE Electronics Express, vol. 17, pp. 20200061, 2020.
[40] S.-L. Jang, Guan-Zhang Li, and Wen-Cheng Lai,” Wide locking range RLC-tank balanced-injection divide-by-5 injection-locked frequency dividers based on harmonic mixing,” IEEE Trans. Microw. Theory Techn., vol. 68, no. 3, pp. 894-903, March. 2020.
[41] S. Jang, W. Lai, G. Li and Y. Chen “High even-modulus injection-locked frequency dividers,” IEEE Trans. on Microw. Theory and Tech., vol. 67, no. 12, pp. 5069-5079, Dec. 2019.
[42] W.-C. Lai, J.-W. Jhuang, S.-L. Jang, G.-Y. Lin, and C.-W. Hsue,“Wide-band injection-locked frequency doubler,” IEEE APCCAS, pp. 265 – 268, 2016.
[43] C.-W. Chang and S.-L. Jang, ”An injection-locked frequency quadrupler in 90 nm CMOS technology,” Microw. Optical Tech. Lett.,55, 2,pp.266-269, Feb. 2013.
[44] S.-L. Jang, J.-J. Chen, C.-C. Liu and M.-H. Juang, ” Injection-locked frequency tripler with series-tuned resonator in 0.13 μm CMOS technology,” Microw. Optical Tech. Lett., pp.1107-1110, May, 2010.
[45] S.-L. Jang, C.-W. Huang, C.-W. Chang, and C.-W. Hsue, ” A parallel-injection Injection locked frequency divider in 0.35 μm SiGe HBT process,” Microwave Opt Tech Lett ., pp.379-383, Feb., 2012.
[46] V. Jain, B. Javid, and P. Heydari, “A BiCMOS dual-band millimeterwave frequency synthesizer for automotive radars,” IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2100–2113, Aug. 2009.
[47] S.-L. Jang, R.-K. Yang, C.-C. Liu, and C.-W. Hsue, "A low power SiGe BiCMOS series-tuned divide-by-3 injection locked oscillators," Microw. Optical Tech. Lett., 51, 2239–2242, 2009.
[48] S.-L. Jang, C.-W. Hsu, C.-W. Chang and C.-W. Hsue, ” Wide-band 3 injection locked frequency divider in 0.35 μm SiGe BiCMOS,” Microw. Optical Tech. Lett., pp.609-611, March, 2011.
[49] C.-C. Liu, C.-C. Wang, S.-L. Jang, and M.-H. Juang,” A SiGe injection-locked-oscillator using HBT injector operated in saturation region,” Microw. Optical Tech. Lett., pp.734-737, April, 2011.
[50] S.-L. Jang, C. C. Liu, and C.-W. Chung, “A tail-injected divide-by-4 SiGe HBT injection locked frequency divider,” IEEE Microw. Wireless Compon. Lett., pp. 236–238, Apr. 2009.
[51] L. Wang, Y. Z. Xiong, S. M. Hu, and T. G. Lim, "A 0.13-μm HBT divide-by-6 injection-locked frequency divider," 2011 IEEE ASSC Conf, Nov. 2011, pp.97-100.
[52] E. Ojefors, B. Heinemann, and U. Pfeiffer, “A 325 GHz frequency multiplier chain in a SiGe HBT technology,” in Proc. IEEE RFIC Symp., 2010, pp. 91–94.
[53] A. Nikpaik, A. H. Masnadi Shirazi, A. Nabavi, S. Mirabbasi, and S. Shekhar, “A 219-to-231 GHz frequency-multiplier-based VCO with 3% peak DC-to-RF efficiency in 65-nm CMOS,” IEEE J. Solid-State Circuits, vol. 53, no. 2, pp. 389–403, Feb. 2018.
[54] S. Kim, P. S. Gudem and L. E. Larson, "A 44-GHz 8-element phased-array SiGe HBT transmitter RFIC with an injection-locked quadrature frequency multiplier," 2010 IEEE Radio Freq. Integr. Circuits Symp., Anaheim, CA, 2010, pp. 453-456.
[55] C. Wang, Z. Chen and P. Heydari, “W-band silicon-based frequency synthesizers using injection-locked and harmonic triplers,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 5, pp. 1307–1320, May 2012.
[56] Y.-H. Chuang, S.-H. Lee, R.-H. Yen, S.-L. Jang, J.-F. Lee, and M.-H. Juang, “A wide locking range and low voltage CMOS direct injection locked frequency divider,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 5, pp. 299–301, May 2006.
[57] J. Jeong and Y. Kwon, “V-band high-order harmonic injection-locked frequency-divider MMICs with wide bandwidth and low-power dissipation,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 6, pp. 1891-1898, Jun. 2005.
[58] S.-L. Jang, G.-Z. Li, and W.-C. Lai,” Wide locking range RLC-tank balanced-injection divide-by-5 injection-locked frequency dividers based on harmonic mixing,” IEEE Trans. Microw. Theory Techn., vol. 68, no. 3, pp. 894-903, March. 2020.