近年來固態硬碟因其體積小、高耐震、低功耗、快速隨機存取等優點，已經廣泛的被當作主要的儲存裝置，然而現今固態硬碟為了增加儲存空間，降低成本，而使得讀寫速度變為緩慢，因此近年來固態硬碟已經發展了很多內部的平行化設計，但是平行化的利用率卻不高，其中一個造成低晶片利用率的主要原因就是存取衝突的問題，進而導致固態硬碟整體的系統效能下降。
本篇論文提出了混合式要求合併方法(HYC)，先透過靜態要求合併演算法處理讀取和寫入要求大部份的存取衝突之後，為了更進一步的將晶片的存取度達到最佳化和最小化存取衝突，針對寫入要求設計了動態要求合併演算法，先進入動態存取最佳化測試，然後根據使用者的系統效能需求去動態調整容忍值，之後利用動態分配方法去重新分配寫入要求的資料位址，再合併去產生更多滿載晶片存取度的寫入群，最後產生的合併群平行的存取到固態硬碟，提升系統整體的效能和輸出。
實驗結果顯示，混合式要求合併方法無論在存取衝突的減少、固態硬碟中快閃記憶體晶片的平行化以及使用率和存取要求的延遲時間上皆有顯著地改善，在讀取要求部分，與PIQ能達到相同的效能之外，在寫入要求部分，隨機的小容量檔案下與PIQ相比在延遲時間上減少了91%、寫入效能和晶片存取度增幅皆達到4倍、滿載的晶片存取度數量增幅更高達74倍。因此本篇所提出混合式要求合併方法在隨機且容量小的檔案下相較於PIQ更能有效的改善寫入的效能和減少衝突問題，使固態硬碟中快閃記憶體晶片的平行度以及晶片存取度達到最佳化。

In recent year ,Solid state drives(SSDs)has been widely used as primary storage device ,the reasons including its non-volatility , lightweight , high performance , low power consumption and shock resistance. In order to improve performance, SSDs are constructed with a number of channels with each channel connecting to a number of NAND flash chips. Despite the rich parallelism of SSD has been exploited, but the utilization of flash chip is seriously low, and one of the main reasons is access conflict between requests, and then will degrade the performance of SSD.
In this paper, we proposed a hybrid I/O request combination (HYC) for minimize access conflict. First, we use static request combination to solve most of the conflict between requests. Second, in order to achieve the optimization of chip access degree and minimization of access conflict, we design dynamic request combination for write request to assign its chip location to another, and then produce combine groups to access SSD in parallel.
The experiments results shows that HYC can achieve the same read performance like PIQ. In the small random file compare with PIQ, HYC reduce 91% write latency and increase the write throughput and chip access degree up to 4 times, and the full chip access degree number as much as 74 times. These results show that HYC is better than PIQ to minimize access conflict and optimize the chip access degree, and achieve higher flash chip parallelism and write performance in SSD.

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