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研究生: 蕭祐杰
You-Jie Siao
論文名稱: 基於IEEE 802.15.4a/z 之低延遲里德-所羅門解碼器架構設計與實現
Design and Implementation of Low Latency Reed-Solomon Decoder Architecture for IEEE 802.15.4a/z IR-UWB System
指導教授: 沈中安
Chung-An Shen
口試委員: 吳晉賢
林昌鴻
黃琴雅
沈中安
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2023
畢業學年度: 112
語文別: 英文
論文頁數: 42
中文關鍵詞: 里德-所羅門碼低延遲IEEE 802.15.4a/zHRP UWB PHY
外文關鍵詞: IEEE 802.15.4a/z, HRP UWB PHY, Reed-Solomon Code, Low Latency, Area efficient
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脈衝超寬頻(IR-UWB)是近年來越來越受到矚目與重視的先進通訊技術。該技術最特別之處在於透過發送奈秒級的脈衝訊號進行通訊,因此,非常適合應用於需要公分級精準度的測距等相關應用。脈衝超寬頻具體應用包括室內定位、免持鑰匙、物品搜尋等。目前已經商用化的產品例如Apple的Air Tag內的U1晶片等也是基於脈衝超寬頻技術。脈衝超寬頻應用的共通之處即為需要對當下環境的情況進行即時反應,否則這些應用將無法發揮效果,因在設計脈衝超寬頻系統時,如何達到低處理延遲是最重要的設計考量,以達到應用系統的即時反應的需求。里德-所羅門碼是超寬頻系統中經常使用的錯誤更正碼,其主要功能為增加冗餘位元讓封包具可修復性,以有效降低封包在傳輸過中因受到干擾而無法正確接收的情況。里德-所羅門碼的元件對於脈衝超寬頻系統整體運算效能有重大影響,因此值得研究探討。本論文基於IEEE 802.15.4a/z規格的脈衝超寬頻系統接收器,設計低延遲與低複雜度的的里德-所羅門碼電路架構。我們提出的架構首先基於平行處理以達到低延遲的運算。此外,由於平行化架構使得電路面積上升,我們進一步也提出了降低面積負責度的電路設計。我們設計的里德-所羅門碼電路架構可以使延遲降低85.7%,而所花費的面積可以降低30%。


Impulse Radio Ultra-Wideband (IR-UWB) communication technology has gained increasing attention recently. Its distinct feature is that it utilizes nanosecond-level pulses for communication. Therefore, UWB is particularly well-suited for developing applications related to distance measurement, with precision that can even reach centimeter-level accuracy. Relevant applications include indoor positioning, keyless entry, and item tracking. Commercial products incorporating UWB technology, such as Apple's AirTag with the U1 Chip, are already available. The common requirement among these applications is real-time responsiveness to the current environmental conditions. Without low-latency design, these applications would not be able to function effectively. Therefore, low latency is crucial for UWB systems. RS codes in UWB systems are responsible for adding redundant bits to make packets error-correctable, effectively reducing the likelihood of packets being incorrectly received due to interference during transmission. Hence, this paper addresses the RS decoder of the IEEE 802.15.4a/z HRP UWB PHY receiver and presents a low-latency architecture through parallelization. In addition, as parallelization increases circuit area, optimized area-efficient circuit designs are proposed. With the implementation of 16-stage parallelization, it reduces latency by 85.7% and achieves a 30% reduction in the required area.

Contents Abstract in Chinese . . . . . . . . . . . . . . . . . . . . . . . . . . iii Abstract in English . . . . . . . . . . . . . . . . . . . . . . . . . . iv Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 IEEE 802.15.4a/z HRP UWB PHY . . . . . . . . . . . . . 5 2.2 Concept of Reed Solomon Codes . . . . . . . . . . . . . . 7 2.2.1 Theoretical RS Codes . . . . . . . . . . . . . . . 9 2.3 Related Work . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.1 General Architecture of RS Decoder . . . . . . . . 19 3 Proposed Reed-Solomon Decoder Architecture . . . . . . . . . 26 3.1 Proposed Low Latency Architecture . . . . . . . . . . . . 26 3.1.1 Parallized Syndrome Computation . . . . . . . . . 26 3.1.2 Parallized Chien Search . . . . . . . . . . . . . . 28 3.2 Proposed Area-Efficient Design . . . . . . . . . . . . . . 29 3.2.1 Method 1: Improve Multiplier . . . . . . . . . . . 29 3.2.2 Method 2: Improve Forney’s Algorithm Architecture 31 4 Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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