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研究生： 許凱勝
Kai-Sheng Hsu
論文名稱： 應用於低延遲通訊網路之高度可調適封包解析電路架構設計與實現
The VLSI Architecture Design of A Highly Configurable Packet Parsing Circuit for Low-Latency Communication Network
指導教授： 沈中安
Chung-An Shen
口試委員: 林昌鴻
Chang-Hong Lin
黃琴雅
Chin-Ya Huang
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2021
畢業學年度： 109
語文別： 英文
論文頁數： 52
中文關鍵詞： 封包解析 、邊緣運算 、網路內處理 、低延遲 、專用集成電路
外文關鍵詞： Packet Parsing, Edge Computing, In-Network Processing, Low Latency, Application Specific Integrated Circuit
相關次數： 點閱：214  下載：1 
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    • 近年來低延遲的網路通訊需求變得越來越重要。邊緣運算聚集了訊息和資源，提供強大的運算能力以及全面性的資料庫，但是物理上傳輸距離的限制導致訊號傳遞上需要較高的傳輸延遲。基於卸載的概念，邊緣運算和網路內處理將部分雲端運算的服務轉移到網絡節點，以減少網絡訊號傳遞所造成的傳輸延遲。在網絡節點中，封包處理是處理網路封包的基本功能。作為封包處理的第一階段，封包解析的性能對任何需要低延遲的應用來說至關重要。這篇論文中提出了一種基於指令集架構的低延遲封包解析器。 實驗結果表明，該架構在處理IPv4和TCP協議的標頭時降低了33.33%的處理延遲。在擷取IGMP協議的Membership Query Message時，該架構提升了46.46%的處理效能。此外，我們進一步提出了新指令和對應的內存結構來減少指令記憶體的資源，能夠降低3.27%到12.35%指令記憶體的面積。

    In recent years, the requirement for low latency network communication is becoming more important. Cloud computing aggregates the information and resource which provides powerful computing capability and comprehensive databases, but the limitation of physical distance causes longer transmission delays. Based on the concept of offloading, edge computing and in-network processing transfer the part of cloud computing services to the network nodes that can reduce the transmission delay in the networks. In the network nodes, packet processing is a fundamental function for handling the network packet. As the first stage of packet processing, the performance of packet parsing is important to meet the requirement of any low latency application. In this work, we present a low latency packet parsing base on the instruction set architecture. The latency of extraction for the header of IPv4 and TCP is reduced by 33.33%. For extracted the Membership Query Message of IGMP, the performance can be improved by up to 46.46%. Further, we propose the new instruction and corresponding memory structure to reduce the resources of instruction memory which can reduce the area by 3.27% to 12.35%.

    摘要 I Abstract II 誌謝 III Table of Contents IV Figures V Tables VI I. Introduction 1 II. Background 7 2.1 The Packet Processing of Network Nodes 7 2.2 Basic Concepts and Operation of Packet Parsing 8 2.3 Related Works 11 III. The Proposed Low-Latency Packet Parsing 15 3.1 Analysis of Timing Schedule for Related Work 15 3.2 The Fundamental of Instruction-based Packet Parsing 19 3.3 The Proposed Instruction Reusing Scheme 21 3.4 The Encoded PHV Instructions 24 IV. The Architecture of The Proposed Low-Latency Packet Parser 26 4.1 The Architectural Overview of the Proposed Parser 26 4.2 The Architecture of the Input Buffer 27 4.3 The Architecture of Extraction Engine 28 4.4 The Architecture of the Output Buffer 30 V. Experimental Results and Comparisons 32 5.1 Implementation Results 32 5.2 Comparison with Related Work 33 VI. Conclusion 39 References 40

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