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研究生: 郭智翔
Chih-hsiang Kuo
論文名稱: 可加倍暫存器之ARM轉譯器
Binary Rewriter for Doubling the Number of Registers on ARM Processor
指導教授: 黃元欣
Yuan-shin Hwang
口試委員: 謝仁偉
Jen-wei Hsieh
黃冠寰
Gwan-hwan Hwang
學位類別: 碩士
Master
系所名稱: 電資學院 - 資訊工程系
Department of Computer Science and Information Engineering
論文出版年: 2012
畢業學年度: 101
語文別: 中文
論文頁數: 49
中文關鍵詞: 加倍暫存器減少暫存器的spill重譯器
外文關鍵詞: binary rewriter, arm, spill reduction
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在這篇paper,我們提出一個可以將arm執行檔加倍其暫存器並且有效的刪除spill指令的工具利用此工具我們平均可以達到5~7%之效果


In this paper, we implement a tool which can doubling the number of arm binary, thus we can remove spill code as possible. We can use this tool to improve the performance about 5 ~ 7%

論文摘要 2 致謝 3 目錄 4 圖目錄 5 表目錄 6 第一章 序論 7 1.1 研究背景 7 1.2 研究動機 7 1.3 研究目的 9 1.4 研究方法 9 1.5 論文架構 10 第二章 文獻回顧 11 2.1 微處理器硬體架構 11 2.2 增加暫存器數目相關 14 2.2.1 Change Register Bank 14 2.2.2 Trading conditional execution 15 2.2.3 指令編碼方式 16 2.2.4 加入 THUMB II IT 指令 20 2.3 Diablo Binary Rewriter 24 第三章 方法 25 3.1 執行流程 25 3.2 消除spill指令 26 3.2.1 找尋區域變數所對應到的stack slots 28 3.2.2 找尋各個 stack slot 對應到的 load/store 指令 29 3.2.3 找尋各個 stack slot 對應到的spill 指令 31 3.2.4 消除 spill 指令 34 3.3 利用 IT指令轉換conditional指令為 unconditional 36 第四章 實驗結果 38 4.1 實驗平台 38 4.2 效能評估 38 第五章 結論 45 5.1 結論 45 5.2 未來展望 45 參考文獻 46

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