在先進通訊系統，光電積體電路扮演決定性角色，達到面積小、高效率、資料傳輸容量大增，對於光電積體電路領域，重要光電元件例如光調制器、分光器、濾波器、可調式光衰減器、光開關，都使用絕緣層上覆矽(SOI)為基板，與CMOS標準製程相容，研發次微米製程，製程極限縮小到線寬0.4 μm彎曲半徑36 μm，長遠目標為在絕緣層上覆矽基板，發展高密度光電積體電路，期望降底成本、減少面積與重量，以達到未來光學元件和積體電路的單石積成(Monolithic Integration)。
在光通訊系統，傳送資訊的資料量、聲音、和影像，可以藉由矽光電調制器由電領域轉換成光領域傳送到目的。本論文設計和研製馬克-詹德干涉儀在絕緣層上覆矽晶圓上，干涉儀的一端製作p-i-n二極體，在p-i-n二極體上加金屬電極，藉由順偏壓產生擴散電流，逆偏壓產生漂移電流，影響載子在p-i-n二極體的動態分佈，達到改變矽光電調制器，調制效率Vπ、以及速度響應。
由於次微米元件面積較小，所以在新竹國家奈米元件實驗室(National Nano Device Laboratories)研發CMOS標準製程與光學微影技術，在台灣大學奈米機電系統研究中心研發晶圓切割技術，調制器的設計、研磨製程等所有技術開發均在台灣科技大學光電積體電路實驗室研發。光調制器共使用六道光罩來定義圖形，使用I-Line Stepper完成黃光製程。
矽線波導線寬0.5 μm蝕刻深度0.21 μm，波導傳輸損耗10.14 dB/cm，量測元件p-i-n二極體IV、CV特性曲線，可推測順偏壓形式Vπ:0.82 V，逆偏壓形式Vπ:8 V，推測速度響應順偏壓1.7 GHz，逆偏壓形式62 GHz。

In the prevailing communication system, optoelectronic integrated circuit (OEIC) plays a crucial role to attain the compact size, high efficiency, and large transmission data capacity. Among OEIC technologies, a silicon-on-insulator (SOI) platform, compatible with the standard manufacture process of complementary metal oxide semiconductor processing (CMOS), was successfully demonstrated on the key photonic components, such as optical modulator, power splitter, wavelength filter, variable optical attenuator, and optical switch. With the favor of the submicron SOI wafer quality improvement for CMOS processing, a critical dimension and bending radius of a silicon wire waveguide can be further reduced to 0.4μm and 36μm, respectively. Our ultimate goal is to develop highly integrated photonic and electronic circuitry on a SOI chip for size, weight, and cost reduction in traditional optical systems for future monolithic integration between photonics and electronics.
In the optical telecommunications, the information of data, voice, and video can be encoded into the optical domain by optical modulator and transmitted to the destination. In this dissertation, the Mach-Zehnder interferometer (MZI) was designed and fabricated on SOI platforms. Then a p-i-n diode coated with metal pads on one arm of MZI was generating diffusion and drift currents, respectively, by forward and reverse biases, which dynamically dominate carriers distribution in a diode and furthermore illustrate the modulator efficiency Vπand speed response.
Due to the small footprint in the submicron dimension, the photolithography was extensively developed at National Nano Device Laboratories (NDL) in Hsinchu city for full compatibility with CMOS. The wafer dicing was accomplished in the Nano-Electro-Mechanical-Systems Research Center of National Taiwan University. The research on the performance design, characterization, and the back-end polishing processing were all developed in the OEIC group of National Taiwan University of Science and Technology. Six layers of photomasks were utilized to define patterns using I-Line stepper for delivering a complete set of optical modulator.
The silicon wire propagation loss was demonstrated as 10.14 dB/cm on a waveguide width of 0.5μm and etch depth of 0.21μm. From the experimental data of IV and CV curves, the Vπ can be derived to be 0.82 V and 8 V, respectively, for forward and reverse biases. Finally the speed response of our silicon wire optical modulator can also be estimated as1.7 GHz in forward bias and improved to be 62 GHz in reverse bias.

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