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研究生: 呂騰傑
Teng-chieh Lu
論文名稱: 升壓型功率因數修正器之類比乘法器研製
Design of an Analog Multiplier for Boost Power Factor Corrector
指導教授: 羅有綱
Yu-kang Lo
邱煌仁
Huang-jen Chiu
劉邦榮
Pang-jung Liu
口試委員: 歐勝源
Sheng-yuan Ou
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2012
畢業學年度: 100
語文別: 中文
論文頁數: 68
中文關鍵詞: 功率因數修正器類比乘法器超高壓製程
外文關鍵詞: power factor corrector, analog multiplier, ultra-high voltage
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  • 近年來功率因數修正器在交換式電源供應器中扮演相當重要的角色。本論文提出一個可用於功率因數修正器的類比乘法器。此乘法器將輸入電壓與回授電壓相乘得到的訊號,來控制輸入電流。本論文將可變線性電阻應用於非反相放大器,藉由改變輸入電壓可以控制可變電阻大小,來改變非反相放大器的電壓增益,如此即可實現乘法器。相較於其他文獻,本論文所提出的乘法器具有較大的輸入範圍,且為單端輸入單端輸出。
    本晶片使用TSMC 0.5-μm 800 V超高壓製程來實現,晶片大小為3.56×2.56 mm2。輸入電壓範圍為交流90至264 V,輸出電壓為400 V。外接電感感值為2 mH,外接電容容值為10 μF,本晶片最小的操作頻率為30 kHz。模擬結果顯示,當誤差放大器輸出電壓從2.5 V~5 V時,乘法器的總諧波失真皆小於4%。


    In recent year, power factor correctors play an important role in switching power supplies. This thesis proposes an analog multiplier that can be applied to power factor correctors. The input current is controlled with the multiplier output, which is obtained by multiplying the input voltage and voltage feedback. The proposed analog multiplier is realized with a variable linear resistor applied to a non-inverting amplifier, whose voltage gain is tuned with the input voltage to control the value of the variable linear resistor. Compared with previous works, the proposed multiplier has the advantages of a large input range and single-ended input to single-ended output.
    This chip had been fabricated with TSMC 0.5-μm 800 V ultra-high voltage process, and its size is 3.56×2.56 mm2. The input voltage is from AC 90 V to 264 V and the output voltage is 400 V. The off-chip inductance is 2 mH, the output capacitance is 10 μF, and the minimum operation frequency is 30 kHz. Simulation results show that the total harmonic distortion of the multiplier is less than 4% when output voltage of the error amplifier is from 2.5 to 5 V.

    摘要 ABSTRACT 誌謝 目錄 圖目錄 表目錄 第一章 緒論 1.1 研究動機與目的 1.2 研究內容 1.3 內容大綱 第二章 功率因數修正器 2.1 功率因數修正器的意義 2.2 功率因數修正器種類 2.3 主動功率因數修正器 2.4 功率因數修正器之操作模式 2.4.1 電壓隨耦控制模式 2.4.2 平均電流控制模式 2.4.3 峰值電流控制模式 第三章 類比乘法器 3.1 一般類比乘法器原理 3.2 可變線性電阻乘法器 第四章 電路設計與分析 4.1 系統架構與原理 4.2 電路設計 4.2.1 疊接轉導放大器 4.2.2 類比乘法器 4.2.3 領先邊緣遮罩 4.2.4 遲滯比較器 4.2.5 零電流偵測電路 4.2.6 緩衝器 第五章 晶片模擬結果 5.1 晶片佈局 5.2 電路模擬結果與分析 5.2.1 輸出波形模擬 5.2.2 乘法器總諧波失真模擬 5.2.3 功率因數模擬 第六章 結論與未來展望 6.1 結論 6.2 未來展望 參考文獻

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