電子產品的發展日新月異，使得功率積體電路的應用越來越廣泛。 功率金氧半場效電晶體具有高輸入阻抗、高切換速度、小的元件尺寸、以及可承受大電壓和大電流的優點，因此是最常應用在功率積體電路的元件之一。 然而，傳統平面式功率金氧半場效電晶體有高導通阻抗的問題。 本論文提出以鰭式結構之橫向雙擴散功率金氧半場效電晶體，以達到適用於電路積體化的橫向式結構和改善元件高導通阻抗的問題。 本文利用Sentaurus TCAD元件模擬軟體進行模擬分析，模擬結果顯示在相當的耐壓條件和佈局面積下，N型基板之鰭式結構功率金氧半場效電晶體相較於傳統平面式功率金氧半場效電晶體有較低的特徵阻抗。 在閘極偏壓為15.0伏特時，其特徵阻抗降低了53.7 %。 原因為鰭式結構使閘極可控制的區域變大，使元件通道的有效寬度變大。 本文也探討了不同元件尺寸對元件電性的影響，在相同佈局面積下，元件尺寸為FW 0.6 um / FH 1.5 um的鰭式結構功率金氧半場效電晶體可以提供最高的導通電流密度，為最優化的元件尺寸。
此外，改以P型基板設計鰭式結構功率金氧半場效電晶體，亦可以有效地降低漂移區高導通阻抗的問題，這是因為此元件的導通阻抗反應在漂移層(N- drift layer)上，而不是在基板上，經由電荷補償的結果可以使用較高摻雜濃度的漂移層；在大約耐壓40伏特和閘極偏壓為15.0伏特時，使用優化元件尺寸的P型基板鰭式結構功率金氧半場效電晶體其特徵阻抗相較於傳統平面式功率金氧半場效電晶體降低了69.7%。

With the development of electronic products continuing to advance, the applications of power integrated circuits (PICs) have become more extensive. The power MOSFET provides advantages such as high input impedance, high switching speed, compact device size, and the capability to sustain high breakdown voltage and high operating current. Thus, it is one of the most commonly used power devices in PICs. However, conventional planar power MOSFET suffers high on-state resistance. In this thesis, fin-based lateral power double-diffused metal–oxide–semiconductor field-effect transistor is proposed in order to provide a lateral device structure applicable for circuit integration and achieve reduction in on-state resistance. Computer-aided design tool Sentaurus TCAD is used to help the development of the designed device. Simulation results show that fin-based power MOSFET with n-type substrate can result in lower specific on-resistance when compared to conventional planar device, with comparable breakdown voltage and same layout area. When the device is operated at a gate bias of 15.0 V, a reduction of specific on-resistance by 53.7% is achieved. The usage of fin-based structure provides the gate to have control in three sides of the channel, which increases the effective channel width of a device.
Dependence of electrical characteristics on fin dimension is also analyzed. For a specific layout area, the highest current density of fin-based power MOSFET is observed at FW 0.6 um / FH 1.5 um, which is then set as the optimized fin dimension. Moreover, the device can further achieve reduction in on-state resistance with the usage of p-type substrate. Attributed to the fact that on-state resistance is associated with the drift layer (N- drift layer) instead of substrate. Fin-based power MOSFET with p-type substrate at FW 0.6 um / FH 1.5 um shows a reduction of specific on-resistance by 69.7% without degradation of blocking voltage when compared to conventional planar device at a gate bias of 15.0 V.

[1] B. Yang, J. Wang, S. Xu, J. Korec and Z. J. Shen, "Advanced Low-Voltage Power MOSFET Technology for Power Supply in Package Applications," IEEE Transactions on Power Electronics, vol. 28, no. 9, 2013, pp. 4202-4215
[2] K. Wei, D. D. -C. Lu, C. Zhang, Y. P. Siwakoti, J. L. Soon and Q. Yao, "Modeling and Analysis of Thermal Resistances and Thermal Coupling Between Power Devices," IEEE Transactions on Electron Devices, vol. 66, no. 10, 2019, pp. 4302-4308
[3] T. Ye and K. W. A. Chee, "Low on-resistance power MOSFET design for automotive applications," IEEE International Conference on ASIC (ASICON), 2015, pp. 1-4
[4] S. Mukherjee, "Power integrated circuits and their applications in power conversion systems," Conference Record Southcon, 1994, pp. 534-539
[5] D. Disney and Z. J. Shen, "Review of Silicon Power Semiconductor Technologies for Power Supply on Chip and Power Supply in Package Applications," IEEE Transactions on Power Electronics, vol. 28, no. 9, 2013, pp. 4168-4181
[6] Y. Zhang and T. Palacios, "(Ultra)Wide-Bandgap Vertical Power FinFETs," IEEE Transactions on Electron Devices, vol. 67, no. 10, 2020, pp. 3960-3971
[7] T. Ogura, "Recent technical trends and future prospects of IGBTs and power MOSFETs," International Power Electronics Conference, 2014, pp. 2068-2073
[8] L. Sun, B. Duan, Y. Wang and Y. Yang, "Analysis of the Fast-Switching LIGBT With Double Gates and Integrated Schottky Barrier Diode," IEEE Transactions on Electron Devices, vol. 66, no. 6, 2019, pp. 2675-2680
[9] E. K. C. Tee et al., "200 V Superjunction N-type Lateral Insulated-Gate Bipolar Transistor With Improved Latch-Up Characteristics," IEEE Transactions on Electron Devices, vol. 60, no. 4, 2013, pp. 1412-1415
[10] F. Yang et al., "A Novel IGBT Structure With Floating N-Doped Buried Layer in P-Base to Suppress Latch-Up," IEEE Electron Device Letters, vol. 37, no. 9, 2016, pp. 1174-1177
[11] S. Guo, H. Huang and X. B. Chen, "Study of the SOI LDMOS With Low Conduction Loss and Less Gate Charge," IEEE Transactions on Electron Devices, vol. 65, no. 4, 2018, pp. 1645-1649
[12] T. Thornton, "High Breakdown Voltage MESFETs Integrated with SOI CMOS Technologies," IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2019, pp. 1-1
[13] I. C. Kizilyalli, Y. A. Xu, E. Carlson, J. Manser and D. W. Cunningham, "Current and future directions in power electronic devices and circuits based on wide band-gap semiconductors," IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA), 2017, pp. 417-417
[14] S. Wirths et al., "Vertical Power SiC MOSFETs with High-k Gate Dielectrics and Superior Threshold Voltage Stability," International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2020, pp. 226-229
[15] S. Dimitrijev, "SiC power MOSFETs: The current status and the potential for future development," IEEE International Conference on Microelectronics (MIEL), 2017, pp. 29-34
[16] F. R. Pierret, Semiconductor Device Fundamentals, Addison-Welsley Publishing Company, 1996
[17] D. A. Neamen, Semiconductor Physics and Devices, McGraw-Hill Education Publishing Company, 2012
[18] Hui Zhao, Yee-Chia Yeo, Subhash C. Rustagi, and Ganesh Shankar Samudra, "Analysis of the effects of fringing electric field on FinFET device performance and structural optimization using 3-D simulation," IEEE Transactions on Electron Devices, vol. 55, no.5, 2008, pp.1177-1179