本篇論文提出四種不同架構的注入鎖定除頻器，分別為使用線性混波技術的三共振RLC共振腔除四注入鎖定除頻器、雙頻同時振盪的除二注入鎖定除頻器、使用電流再利用架構的除四注入鎖定除頻器及使用電流再利用架構的除八注入鎖定除頻器，並全部實現於台積電(TSMC) 0.18 μm製程。
首先，提出一個使用線性混波技術的三共振RLC共振腔除四注入鎖定除頻器，並由台積電(TSMC) 0.18 μm製程實現。因為三共振RLC共振腔及重疊的除頻範圍，使此除四除頻器設計有著較寬的除頻範圍。當工作偏壓在1伏特、注入強度為0 dBm時，注入鎖定訊號範圍為8.4 GHz ~ 13.5 GHz，百分比為46.58 %。此除頻器核心功率消耗為9.86毫瓦，晶片面積為0.985 × 0.836 mm2。
其次，提出一個雙頻同時振盪的除二注入鎖定除頻器，並由台積電(TSMC) 0.18 μm製程實現。此除頻器由兩組分別操作在3.7 GHz和5.1 GHz的子除頻器組成。透過控制供應電壓，使除頻器操作在高頻段、低頻段及同時發生雙頻段模式。此除頻器有效瞭解多共振LC注入鎖定除頻器的操作模式。在寬鎖頻下的品質因子為27.96，注入強度為0 dBm時的注入鎖定訊號範圍為5.63 GHz ~ 11.89 GHz，百分比為71.46 %，核心功率消耗為2.556毫瓦。在低功耗下的品質因子為48.8，注入強度為0 dBm時的注入鎖定訊號範圍為5.71 GHz ~ 7.95 GHz，百分比為32.8 %，核心功率消耗為0.672毫瓦。此晶片面積為0.65 × 1.023 mm2。
接著，提出一個使用電流再利用架構的除四注入鎖定除頻器，並由台積電(TSMC) 0.18 μm製程實現。此除四除頻器架構概念是利用一組除二N型金氧半場效電晶體交互式耦合除頻器工作後，將輸出訊號拉至另一組除二N型金氧半場效電晶體交互式除頻器來有效提升除頻範圍。在當工作偏壓在1.6伏特、注入強度為0 dBm時，注入鎖定訊號範圍為9.82 GHz ~ 16.69 GHz，百分比為51.83 %。此除頻器核心功率消耗為16.288毫瓦，晶片面積為0.644 × 0.91 mm2。
最後，提出一個使用電流再利用架構的除八注入鎖定除頻器，並由台積電(TSMC) 0.18 μm製程實現。此除四除頻器架構概念是利用一組除四N型金氧半場效電晶體交互式耦合除頻器工作後，將輸出訊號拉至另一組除二P型金氧半場效電晶體交互式除頻器來有效提升除頻範圍。在當工作偏壓在1.7伏特、注入強度為0 dBm時，注入鎖定訊號範圍為16.83 GHz ~ 17.94 GHz，百分比為6.385 %。此除頻器核心功率消耗為9.537毫瓦，晶片面積為0.931 × 1.2 mm2。

In this thesis, four different varieties of injection-locked frequency divider (ILFD): triple-resonance RLC-resonator divide-by-4 ILFD, concurrent oscillating divide-by-2 ILFD, current-reused divide-by-4 LC ILFD and current-reused divide-by-8 LC ILFD.
First, a triple-resonance RLC-resonator divide-by-4 injection-locked frequency divider (ILFD) in the 0.18 μm CMOS process is presented. The locking range of conventional single-stage divide-by-4 LC-tank ILFD is limited due to using harmonic mixer with small frequency conversion gain. The studied linear mixer divide-by-4 ILFDs have wide locking range because of triple-resonance RLC resonator and overlapping locking ranges. At the drain-source bias of 1 V and at the incident power of 0 dBm, the locking range of the triple-resonance ILFD is 5.1 GHz (46.58 %) from 8.4 to 13.5 GHz. The core power consumption is 9.86 mW and the total area including the output buffer and the pads is 0.985 × 0.836 mm2.
Next, a concurrent oscillating divide-by-2 injection-locked frequency divider (ILFD) in the 0.18 μm CMOS process is presented. The ILFD consists of two capacitive cross-coupled sub-ILFDs operate at 3.7 GHz and 5.1 GHz respectively. The two sub-ILFDs are coupled by a pair of MIM capacitors. By controlling the gate voltages of the switching transistors, the ILFD has three different operational modes, high-band dominant mode, low-band dominant mode and concurrent oscillation mode. In the concurrent mode, the free-running ILFD can generate differential signals at 3.7 GHz, 5.1 GHz and their harmonics and other cross-modulation products. At the injection power mode, the locked ILFD outputs only the fundamental and harmonics. At low-injection power mode, the ILFD outputs concurrent oscillating signals in addition to the locked fundamental. The wide-locking-mode figure of merit (FOM) of the ILFD is 27.96 with wide locking range 6.26 GHz from 5.63 to 11.89 GHz. The power consumption is 2.556 mW and the input power is 0 dBm. The low-power-mode figure of merit (FOM) of the ILFD is 48.8 with wide locking range 2.24 GHz from 5.71 to 7.95 GHz. The power consumption is 0.67 mW and the input power is 0 dBm.
After that, a current-reused divide-by-4 LC injection-locked frequency divider (ILFD) implemented in the TSMC 0.18 μm 1P6M CMOS process is proposed. Conventional harmonic mixer divide-by-4 ILFD has limited locking range, and this thesis shows a wide locking range divide-by-4 LC ILFD designed with one linear mixer divide-by-2 n-core cross-coupled ILFD stacked on the top of the other linear mixer divide-by-2 n-core cross-coupled ILFD. At the supply of 1.6 V and at the incident power of 0 dBm, the locking range is 6.87 GHz (51.83 %) from 9.82 to 16.69 GHz. Low power mode is also measured. The free-running oscillation frequency is 3.75 GHz. The core power consumption is 16.288 mW and the die area is 0.644 ×0.91 mm2.
Eventually, a current-reused divide-by-8 LC injection-locked frequency divider (ILFD) designed in the TSMC 0.18 μm CMOS process is proposed. The proposed current-reused ILFD is based on a ÷2 p-core LC ILFD stacking on a ÷4 n-core capacitive cross-coupled LC ILFD. Injection MOSFETS in both ÷2 and ÷4 ILFDs are used as linear mixers. At the supply of 1.7 V and at the incident power of 0 dBm, the locking range is 1.11 GHz (6.385 %), from the incident frequency 16.83 GHz to 17.94 GHz. The core power consumption is 9.537 mW and the die area is 0.931 × 1.2 mm2.

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