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研究生： 林柏辰
Po-Chen Lin
論文名稱： 提升可程式陣列元件系統應用在視覺辨識系統之可靠度設計與實作
Design and Implementation of a Flow Process Lockstep Architecture for a Robust FPGA-Based Visual Inspection System
指導教授： 許孟超
Mon-Chau Shie
口試委員: 阮聖彰
Shanq-Jang Ruan
吳晉賢
Chin-Hsien Wu
林昌鴻
Chang Hong Lin
沈中安
Chung-An Shen
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2013
畢業學年度： 101
語文別： 英文
論文頁數： 32
中文關鍵詞： 即時排程 、工廠流程 、Lockstep
外文關鍵詞： NIOSII, flow process, lockstep
相關次數： 點閱：197  下載：2 
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    • 在這篇論文，我們提出一個強健的系統架構能在極端的工業環境下正常運作，整個系統應用在雙攝影機的視覺辨識的機構上。這個穩定的架構就算遇到外在環境的干擾，讓以FPGA為影像處理晶片的辨識系統能夠更可靠的運行，卻只有增加一點點的額外系統成本，保持在價位上的競爭力。在整個架構的設計上，分為兩個部分，分別為主要的視覺辨識系統與工廠流程控制，以及監控系統；監控系統主要的目的是透過Lockstep的方式以及電源監控的方式讓主系統能夠在遭遇到干擾之後還能正常運作。在軟體的架構上，本篇論文採用即時排程來讓系統重置所需的時間變成可知的，讓工廠流程設計上可以有可靠度的保證。依評估與比較的結果顯示，本研究所提出的可靠度架構為一個應用在工業環境下合適的平台。

    In this work, we present a robust implementation of a hardware and software architecture that applies to a dual camera visual inspection system in an extreme environment of industry. The approach is cost-effective and reliable enough that allows visual inspection system working stably even an unpredictable even occurs.
    The hardware and software design includes two portions, one is visual inspection system for industrial flow process controlling, the other is supervisor sub-system which monitors the power consumption of system and tackles the recovering procedure from system failure. The software architecture uses a real-time scheduling model both side in the field-programmable gate array (FPGA) with NIOSII central processing unit (CPU), and microcontroller (MCU) of supervisor sub-system that optimizes the response time of system recovering from a panic caused by environmental interferences (e.g. voltage spikes or ionizing radiation). The software design also uses a script engine method that lead to a good adaptability to different flow process of visual inspection system. With respect to the state of the art, our work increases the immunity of hardware design in order to against electromagnetic interference (EMI) generated by air solenoid valve and survives from transient discharge or inductive inrush current drop. The estimated results demonstrate that the proposed scheme can achieve a low-cost design which can be employed to practical application but still robust enough.

    摘要………………………………………………………………………………………………………………………..IV Abstract……………………………………………………………………………………………………………………V 致謝……………………………………………………………………………………………………………..…………VI Table of Contents……………………………………………………………………………………………………VII List of Figures……………………………………………………………………………………………………..……IX List of Tables…………………………………………………………………………………………………………..…X I. Introduction 1 II. Related Work 2 2.1 Hardware Lockstep 2 2.2 Triple Modular Redundancy in Lockstep 2 III. Visual Inspection System Architecture 5 IV. System Design 7 4.1 WANG-WANG BOARD Hardware Architecture 7 4.1.1 Power Management 7 4.1.2 Power Monitor AFE 7 4.1.3 SDTV Video Decoder 8 4.1.4 Video DAC 8 4.1.5 Memory 8 4.1.6 External Parallel Interface 9 4.1.7 Supervisor Sub-System 9 4.2 Features of the WANG-WANG BOARD 10 4.3 Lockstep Guarding Ring Architecture 12 4.4 Supervisor Sub-System Hardware Architecture 14 4.4.1 Hercules TMS470M MCU 14 4.4.2 FPGA Power consumption Monitor 14 4.4.3 Self-Supervising 14 4.5 Software Structure 16 4.5.1 Task 16 4.5.2 Supervisory Tasks 16 4.5.3 Flow Process 17 4.5.4 Script Engine 17 4.5.6 Visual Inspection Tasks 18 4.5.7 Scheduler 18 4.5.8 Scheduling Policy Rate-Monotonic Scheduling 18 4.5.9 First Stage Recovery Time Derivation 18 4.5.10 Second Stage Recovery Time Derivation 19 4.6 Hardware Design 20 4.6.1 DDRII SDRAM Memory 20 4.6.2 DDRII SDRAM Controller with ALTMEMPHY 20 4.6.3 DDRII SDRAM Termination Scheme 20 4.6.4 DDRII SDRAM Traces Routing 20 4.5.5 DDRII SDRAM Verification 23 4.6.6 Power Distribution 24 4.6.7 Oscillator Distribuion 25 4.6.8 PCB Stack Design 27 V. Estimation and Comparison 29 VI. Conclusions 31 VII. References 32

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