近年來，深度學習( Deep Learning )作為人工智慧( Artificial Intelligence )及機
器學習( Machine Learning )的一個分支，已經在各個領域展現其強大的影響力。特
別是卷積神經網路( Convolutional Neural Network, CNN )在圖像處理及辨識物體上的
應用，皆有優異的表現。然而要將卷積神經網路實踐在硬體上，則需要考量如何在
有限的硬體資源環境下，降低大量的權重資料讀取，並且同時維持高效率運算。
為了達到上述目的，本論文設計與實現一個基於 EMNIST 資料集之 CNN 加
速器。本論文採用 line buffer 架構，以降低大量的權重資料讀取。為了取得高準確
度並同時保有低參數量的模型，本論文針對幾個常見的卷積神經網路做訓練測試。
最終選擇以 LeNet 為基礎之模型，其準確度達 91.06%，參數量 5810 個。此外為了
更進一步地降低資源使用，運算上以 8 位元整數取代 32 位元浮點數。最後再針對
整體架構做管線化處理，以提升整體工作頻率。
本論文已在 FPGA 及 ASIC 標準元件庫上完成驗證。兩者最大工作頻率皆可
達到 100 MHz，且在 EMNIST 資料集上的測試準確度可達到 90.7%。FPGA 是在
ZYNQ-7000系列的 XC7Z020CLG400-3器件上實現，LUT使用 24196個，LUTRAM
使用 1578 個，FF 使用 28524 個，DSP 使用 220 個。ASIC 部分則是使用 tsmc 0.18
µm 標準元件庫，晶片尺寸為 4828.18 µm x 4824.4 µm，等效邏輯閘數量為 1144076
個。

In recent years, deep learning, a branch of Artificial Intelligence and machine
learning, has demonstrated significant influences on various fields. In particular,
Convolutional Neural Network ( CNN ) has excelled in image processing and object
recognition tasks. However, the hardware implementation on CNN requires addressing
how to reduce the extensive weight data read in a constrained hardware environment while
maintaining high computational efficiency.
To achieve this goal, this thesis designs and implements a CNN accelerator based on
the EMNIST dataset. The design adopts the architecture of the line buffer to reduce the
number of weight data reads. To achieve high accuracy with low parameter models, several
common CNN architectures are trained and evaluated. Ultimately, a model based on LeNet
is selected, achieving an accuracy of 91.06% with 5810 parameters. Furthermore, to further
reduce resource usage, computations are performed using 8-bit integers instead of 32-bit
floating-point numbers. Finally, the overall architecture is implemented by the pipeline
technique to enhance the overall operating frequency.
This thesis has been validated on both FPGA and ASIC standard cell libraries. Both
platforms achieve a maximum operating frequency of 100 MHz, with a test accuracy of
90.7% on the EMNIST dataset. The FPGA implementation is carried out on the
XC7Z020CLG400-3 device from the ZYNQ-7000 series, utilizing 24196 LUTs, 1578
LUTRAMs, 28524 FFs, and 220 DSPs. The ASIC implementation employs the tsmc 0.18
µm standard cell library, with a chip size of 4828.18 µm x 4824.4 µm and an equivalent of
1144076 logic gates.

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