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研究生： 顏嘉威
Chia-Wei - Yen
論文名稱： 每秒一億次取樣之十二位元連續漸進式類比數位轉換器設計與實現
Design and Implementation of a 12-bit 100-MS/s SAR ADC
指導教授： 鍾勇輝
Yung-Hui Chung
口試委員: 陳筱青
Hsiao-Chin Chen
陳亮仁
Liang-Jen Chen
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2017
畢業學年度： 105
語文別： 英文
論文頁數： 80
中文關鍵詞： 連續漸進式類比數位轉換器 、次階漸進式類比數位轉換器
外文關鍵詞： SAR ADC, Sub-ranged SAR ADC
相關次數： 點閱：399  下載：19 
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    • 本論文實現一個十二位元、每秒一億次取樣之連續漸進式類比數位轉換器(SAR ADC)。為了達到每秒一億次取樣的操作速度，使用次階漸進式 (Sub-Ranged SAR)的架構。主要以連續漸進式類比數位轉換器為基礎，搭配次階式架構的運作，用一個解析度較低但速度較快的二元搜尋式(Binary-Search)類比數位轉換器先解出前五個位元的量化結果，來減輕連續漸進式類比數位轉換架構速度慢的缺點。為了滿足十二位元的線性度要求，在數位類比轉換器(DAC)中使用了電容交換的技術，在相同的電容陣列下，可以得到更好的線性度。
    在台積電的65奈米製程下，我們實現了一個十二位元、每秒一億次取樣之連續漸進式類比數位轉換器，晶片面積為0.102 平方毫米。在1.2伏特的操作電壓以及100MHz的取樣頻率下，量測到的動態效能，有效位元(ENOB)為10.0 bit，訊噪失真比(SNDR)為62dB，無雜散動態範圍(SFDR)在使用電容交換技術之後可以達到82dB。而量測到的靜態效能，微分非線性誤差(DNL)為+2.23LSB ~ -0.87LSB，積分非線性誤差(INL)在使用電容交換技術之後為+1.81LSB ~ -1.49LSB。

    This thesis presents a 12bit 100MS/s successive approximation register analog to digital converter (SAR ADC). Sub-ranged SAR architecture is used to achieve 100MS/s sampling rate. This ADC design is based on SAR architecture but with sub-ranged operation. A low resolution and high speed binary-search ADC is used to quantize first five MSBs for speeding up. For 12-bit linearity requirement, capacitor swapping technique is used in digital to analog converter (DAC) to prevent the use of large capacitor array.
    This ADC was implemented in TSMC 65nm digital CMOS process. The 12-bit ADC occupies an active area of 0.102mm2. At 1.2V supply voltage and 100MHz sampling rate, the measured dynamic performance, ENOB is 10.0 bit and SNDR achieves 62dB. SFDR with capacitor swapping techniques is 82dB. The measured static performance, DNL is from +2.23LSB to -0.87LSB, INL is from +1.81LSB to -1.49LSB.

    論文摘要 i Abstract ii 誌謝 iii Contents iv List of Figures vi List of Table ix Chapter 1 Introduction -1- 1.1 Motivation -1- 1.2 Organization of the Thesis -4- Chapter 2 Sub-Ranged SAR ADC -5- 2.1 Binary-Search Sub-Ranged SAR ADC -6- 2.2 Issue of Binary-Search Sub-Ranged SAR ADC -11- 2.2.1 Reference Gain Difference -11- 2.2.2 Sampling Difference -14- 2.2.3 Offset Difference -16- Chapter 3 Circuit Implementation -21- 3.1 A 5-bit Binary Search ADC -22- 3.1.1 Distributed Sample and Hold Circuit -22- 3.1.2 Coarse Comparator -23- 3.1.3 Resistive DAC -26- 3.2 Sample and Hold Circuit -27- 3.3 Digital to Analog Converter -29- 3.3.1 Capacitor Array Size Decision and Architecture -29- 3.3.2 Up-then-Down Switching -31- 3.3.3 Capacitor Swapping Technique -36- 3.4 Fine Comparator -40- 3.5 SAR Control Logic -42- 3.5.1 Self-Timing Loop -42- 3.5.2 Encoder -44- 3.6 Layout Consideration -46- 3.7 Post-Layout Simulation Results -49- Chapter 4 Measurement Results -50- 4.1 Measurement Environment -51- 4.2 ADC Performance -54- 4.2.1 Dynamic Performance -54- 4.2.2 Static Performance -57- 4.2.3 Improvements by Capacitor Swapping Scheme -58- 4.3 Analysis and Brief Summary -60- Chapter 5 Conclusion -63- 5.1 Conclusion -63- 5.2 Future Work -64- Reference -65-

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