本論文分成兩部分, 第一部分使用了台積電 0.18 μm 1P6M 互補式金氧化物半導體製程實現適用於生理檢測之雙旁通窗逐漸逼近式轉換器，±32 旁通窗是通過電流相關器特性與動態鄰近比較器一起實現，±256 旁通窗是通過次類比數位轉換器實現，它僅在輸入信號沒有 ±32 旁通窗大小時才運行第一階段，因此雙旁通窗機制可以感測更多種類之信號並保持低功耗。此外，利用數位合成在片內實現校準狀態機及透過片內 W-2W 數位類比轉換器以提供雙旁通窗所需之電壓，使晶片能夠自動校準雙旁通窗大小。10 位元，採樣率為 100kS/s，輸入頻率在奈奎斯 (49kHz) 時，在 0.6 V 電源電壓和有效位元 (ENoB) 為 9.0629 位元的情況下，測得的信噪比 (SNDR) 和無雜散動態範圍 (SFDR) 分別為 56.3187 和 63.1661 dB，類比數位轉換器 (ADC) 消耗功耗為 349.86 nW，品質因數 (FoM) 約為 6.54 fJ/conv.-step，ADC 晶片核心面積為 412 X 282.46 μm2。

論文的第二部分是自主電流自適應 ADC 輸入驅動器 (ACAID)。提議的ACAID 電流將隨著電壓輸出顯著變化以增加迴轉率而自主增加。當電壓差接近平衡值時，高電源電流將逐漸恢復到低靜態電流。該電路還使用懸浮閘技術來提供電路可編程性。此外，ACAID 可以構造成全差分電容電荷放大器，不會造成額外的靜態功耗，使電路起到自適應電源的作用。ACAID 結合了編程電路和採樣頻率為 200kS/s 的 10 位元 SAR ADC，採用台積電 0.35μm 2P4M 互補氧化金半導體工藝實現製造。通過將相當於 0.5pF 的 ADC 負載加到 ACAID 的輸出端，在 2.8Vpp的輸入振幅和 100kHz 的輸入頻率下，總諧波失真達到-70.1dB。ADC 在奈奎斯特速率下測得的 SNDR 和 SFDR 分別為 56.51dB 和 60.53dB，測得的 ENoB 約為 9.1位。當輸入頻率增加和跟踪時間減少時，所提出的 ACAID 將比傳統的望遠鏡放大器節省更多的功率。當輸入頻率為 100kHz 且跟踪佔空比為 10% 時，原型驅動電路可節省 49.5% 功耗。當輸入頻率為 1MHz，跟踪時間僅佔整個週期的 10%時，節電率為 76.2%。

本篇論文最後另外介紹另一種可重構的差分轉單端自主電流自適應緩衝放大器 (ACABA)。ACABA 透過懸浮閘的技術，其輸出直流電平和帶寬可以透過編程浮動節點上的電荷來調節。在不改變輸出直流電平的情況下，可以通過切換不同數量的電容器來改變增益。在沒有額外的傳感和控制電路的情況下，當輸入信號變化很快或很大時，所提出的 ACABA 的電流消耗會自發增加，從而實現高轉換率。當輸出電壓達到平衡時，電源電流自動減小回低靜態電平。因此，所提出的 ACABA 是節能的，適合處理生理信號。當加載一個 10 pF 電容器時，它消耗3 µW 以實現 100 kHz 的單位增益帶寬，測得的 IIP2 值為 52.66 dBV，轉換速率為7.86 V/μs。ACABA 已於 2021 年發表於 TBioCAS 期刊，然而因在設計中所觀察到轉換率瓶頸的問題，額外提出了一種瞬態增強型電路，整體增強了 ACABA 的瞬態響應，從而實現了更快的階躍響應、更高的電源效率以及良好的線性度。所提出的電路採用 0.35 μm CMOS 工藝設計並製造了原型芯片。根據測量結果，所提出的電路將建立時間縮短了 62.1%，將轉換速率提高了 3.1 倍，並將總諧波失真
(THD) 降低了 17 dB，而無需額外的靜態功耗。使用 2.5V 電源電壓時，建議的緩衝放大器允許最大輸入信號幅度為 2.3V，THD 低於 −60dB。此外，與其他最先進的設計相比，增強型緩衝放大器在小信號和大信號性能方面均表現出最佳功率效率。

This thesis is divided into two parts, the first part implements a dual bypass-switching-successive approximation(DBSSA) register ADC, which is suitable for biomedical signal sensing, using the TSMC 0.18 μm 1P6M complementary metal oxide semiconductor processes. The ±32 window is implemented with the dynamic proximity comparator through the current correlator characteristic. The ±256 window is implemented with the sub-ADC, which only operate when the input signal is without the ±32 window size at the first phase, so the dual bypass window can sense more kind of signals and maintain the low power consumption. Besides, a calibration state machine is implemented on-chip using digital synthesis and the on-chip W-2W digital-to-analog converter so that the chip can automatically calibrate the dual bypass window size. The 10-bit 100kS/s input frequency at Nyquist rate (49 kHz), with a supply voltage of 0.6 V and the Effective Number of Bits (ENoB) is 9.0629-bit, the measured signal-to-noise-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 56.3187 and 63.1661 dB. The ADC consumes power is 349.86 nW. The figure of merit (FoM) is around 6.54 fJ/conv.-step, and the ADC chip core area is 412 × 282.46 μm2.

The second part of the thesis is the autonomous current adaptive ADC input driver
(ACAID). The proposed ACAID current will increase autonomously as the voltage output changes significantly to increase the slew rate. The high power supply current will
gradually recover to the low quiescent current when the voltage difference is close to the equilibrium value. The circuit additionally uses floating gate technology to provide circuit programmability. In addition, ACAID can be constructed as a fully differential capacitive charge amplifier, which does not cause additional static power consumption, and enables the circuit to function as an adaptive power supply. The ACAID combines a programming circuit and a 10-bit SAR ADC with a sampling frequency of 200kS/s, which are implemented and manufactured using TSMC’s 0.35 μm 2P4M complementary gold oxide semiconductor process. Through the ADC load equivalent to 0.5pF added to the output of ACAID, the total harmonic distortion reaches -70.1dB under an input amplitude of 2.8Vpp and input frequency of 100kHz. The SNDR measured by the ADC at the Nyquist rate and SFDR are 56.51dB and 60.53dB, respectively, and the measured ENoB is about 9.1 bits. When the input frequency increases and the tracking time decreases, the proposed ACAID will save more power than the traditional telescope amplifier. The prototyped driver circuit can save 49.5% power consumption when the input frequency is 100 kHz with a 10% duty cycle for tracking. When the input frequency is 1MHz and the tracking time only accounts for 10% of the overall cycle, the power saving rate is 76.2%.

Another reconfigurable differential-to-single-ended autonomous current-adaptive buffer amplifier (ACABA) is introduced at the end of this thesis. ACABA uses floating gate technology, and its output DC level and bandwidth can be adjusted by programming the charge on the floating node. The gain can be varied by switching different numbers of capacitors without changing the output DC level. Without additional sensing and control circuits, the current consumption of the proposed ACABA increases spontaneously when the input signal changes quickly or greatly, thus achieving a high slew rate. When the output voltages are balanced, the supply current is automatically reduced back to a low quiescent level. Therefore, the proposed ACABA is energy-efficient and suitable for processing physiological signals. When loaded with a 10 pF capacitor, it dissipates 3 µW to achieve a unity-gain bandwidth of 100 kHz, with a measured IIP2 value of 52.66 dBV and a slew rate of 7.86 V/μs. ACABA has been published in TBioCAS journal in 2021. However, due to the conversion rate bottleneck problem observed in the design, an additional transient enhancement circuit is proposed, which enhances the transient response of ACABA as a whole, thereby achieving faster order jump response, higher power efficiency, and good linearity. The proposed circuit was designed and a prototype chip was fabricated in a 0.35 μm CMOS process. According to the measured results, the proposed circuit shortens the settling time by 62.1%, increases the slew rate by a factor of 3.1, and reduces the total harmonic distortion (THD) by 17 dB without requiring additional static
power consumption. The proposed buffer amplifier allows a maximum input signal amplitude of 2.3V with a THD below −60dB when using a 2.5V supply voltage. In addition, the enhanced buffer amplifier exhibits the best power efficiency in both small-signal and large-signal performance compared to other state-of-the-art designs.

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