研究生: |
黃濬杰 Jyun-Jie Huang |
---|---|
論文名稱: |
低功耗之二階強健式多級三角積分類比數位轉換器 A Low Power Second-Order Sturdy-MASH Delta-Sigma AD Converter |
指導教授: |
姚嘉瑜
Chia-Yu Yao |
口試委員: |
陳筱青
Hsiao-Chin Chen 彭盛裕 Sheng-Yu Peng |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電機工程系 Department of Electrical Engineering |
論文出版年: | 2013 |
畢業學年度: | 101 |
語文別: | 中文 |
論文頁數: | 56 |
中文關鍵詞: | 三角積分調變器 、Sturdy-MASH 、多級雜訊頻移 、電容積分器 |
外文關鍵詞: | Switched-Capacitor Integrator, Sturdy-MASH ADC. Multi-stage noise shaping |
相關次數: | 點閱:276 下載:2 |
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生醫科技越來越進步,其中在生醫檢測系統的應用上,資料轉換器扮演著重要的角色,負責將類比訊號轉換成數位訊號,提供後端的微處理機做更進一步的生理訊號分析與處理,而低功率消耗特性在生醫應用晶片更是無可避免的重要規格。類比數位轉換器有許多種類,而三角積分調變器與超取樣技術早被應用於現代的類比數位轉換器,三角積分調變器最大的特色是能將量化雜訊移至高頻端,並使用低通濾波器濾除,達到一個高解析度的數位訊號。
本論文設計了一個應用於生醫之低功率與低電壓三角積分類比數位轉換器。系統採用可操作在低增益的Sturdy-MASH架構,並以反相器(Inverter)取代電容積分器中的運算放大器,實現一個低功耗之二階多級雜訊頻移的三角積分調變器。 晶片使用TSMC 0.18um製程實現,晶片面積包含腳位約0.033 mm2 ,操作電壓為1V,取樣頻率為5.12 MHz,系統訊號頻寬10 kHz,解析度達到11.88bit,功率消耗為28 uW。
In a biomedical signal detecting system, analog to digital converter (ADC) plays an important role to translate biomedical signals from analog to digital for the back-end microprocessor to analyze and process. The low power consumption design is an important specification for biomedical chips.
Among many different types of ADCs, the delta-sigma-modulator (DSM) ADC has a unique characteristic of pushing the quantization noise to high frequencies and conserves the desired signal at the low frequencies. Therefore the quantization noise is easily removed by a low-pass filter. This advantage makes the modulator easily achieve high resolution.
This thesis presents a low power and low voltage DSM ADC for biomedical applications. The system employs the Sturdy-MASH (SMASH) architecture that allows the usage of low gain Op. Amps. On the other hand, the SMASH architecture is insensitive to the offset voltage of the employed Op. Amps. Therefore, we can replace the Op. Amps. by inverters. The chip is designed in TSMC 1P6M 0.18m CMOS technology. The chip area is 0.033 mm2. The chip operates under 1-V power supply and 5.12-MHz sampling clock with 256 over-sampling ratio. The measured resolution is 11.88 bits. The total power consumption of the proposed ADC is 28 uW.
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