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研究生: 黃濬杰
Jyun-Jie Huang
論文名稱: 低功耗之二階強健式多級三角積分類比數位轉換器
A Low Power Second-Order Sturdy-MASH Delta-Sigma AD Converter
指導教授: 姚嘉瑜
Chia-Yu Yao
口試委員: 陳筱青
Hsiao-Chin Chen
彭盛裕
Sheng-Yu Peng
學位類別: 碩士
Master
系所名稱: 電資學院 - 電機工程系
Department of Electrical Engineering
論文出版年: 2013
畢業學年度: 101
語文別: 中文
論文頁數: 56
中文關鍵詞: 三角積分調變器Sturdy-MASH多級雜訊頻移電容積分器
外文關鍵詞: Switched-Capacitor Integrator, Sturdy-MASH ADC. Multi-stage noise shaping
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生醫科技越來越進步,其中在生醫檢測系統的應用上,資料轉換器扮演著重要的角色,負責將類比訊號轉換成數位訊號,提供後端的微處理機做更進一步的生理訊號分析與處理,而低功率消耗特性在生醫應用晶片更是無可避免的重要規格。類比數位轉換器有許多種類,而三角積分調變器與超取樣技術早被應用於現代的類比數位轉換器,三角積分調變器最大的特色是能將量化雜訊移至高頻端,並使用低通濾波器濾除,達到一個高解析度的數位訊號。
本論文設計了一個應用於生醫之低功率與低電壓三角積分類比數位轉換器。系統採用可操作在低增益的Sturdy-MASH架構,並以反相器(Inverter)取代電容積分器中的運算放大器,實現一個低功耗之二階多級雜訊頻移的三角積分調變器。 晶片使用TSMC 0.18um製程實現,晶片面積包含腳位約0.033 mm2 ,操作電壓為1V,取樣頻率為5.12 MHz,系統訊號頻寬10 kHz,解析度達到11.88bit,功率消耗為28 uW。


In a biomedical signal detecting system, analog to digital converter (ADC) plays an important role to translate biomedical signals from analog to digital for the back-end microprocessor to analyze and process. The low power consumption design is an important specification for biomedical chips.
Among many different types of ADCs, the delta-sigma-modulator (DSM) ADC has a unique characteristic of pushing the quantization noise to high frequencies and conserves the desired signal at the low frequencies. Therefore the quantization noise is easily removed by a low-pass filter. This advantage makes the modulator easily achieve high resolution.
This thesis presents a low power and low voltage DSM ADC for biomedical applications. The system employs the Sturdy-MASH (SMASH) architecture that allows the usage of low gain Op. Amps. On the other hand, the SMASH architecture is insensitive to the offset voltage of the employed Op. Amps. Therefore, we can replace the Op. Amps. by inverters. The chip is designed in TSMC 1P6M 0.18m CMOS technology. The chip area is 0.033 mm2. The chip operates under 1-V power supply and 5.12-MHz sampling clock with 256 over-sampling ratio. The measured resolution is 11.88 bits. The total power consumption of the proposed ADC is 28 uW.

摘要 I Abstract II 致謝 III 目錄 IV 圖目錄 VII 表目錄 XI 第一章 概論 1 1.1 前言 1 1.2 研究動機 1 1.3 研究流程 3 第二章 超取樣三角積分調變器原理介紹 4 2.1 介紹 4 2.2 奈奎式取樣定理 4 2.3 量化誤差 5 2.4 超取樣技術 8 2.5 雜訊移頻技術 9 2.6 一階三角積分調變器 11 2.7 二階三角積分調變器 13 2.8 高階三角積分調變器 14 2.8.1 單迴路架構 15 2.8.2 多級雜訊移頻 16 第三章 系統與電路設計 18 3.1 系統設計 18 3.1.1 Sturdy-MASH (smash)架構 18 3.1.2 Simulink 系統模擬 19 3.2 電路非理想效應 24 3.2.1 Clock jitter 24 3.2.2 Finite Opamp Gain 及 Offset 影響 25 3.2.3 熱雜訊(Thermal Noise) 30 3.2.4 非理想效應行為模擬 32 3.3 三角積分調變器電路設計 33 3.3.1 反相器電路設計 33 3.3.2 類比開關設計 36 3.3.3 量化器電路設計 38 3.3.4 非重疊時脈產生器之設計 39 3.4 三角積分調變器系統之電路實現 41 3.5 佈局考量及後模結果 44 3.5.1 晶片佈局 44 3.5.2 佈局後之模擬結果 46 第四章 量測結果 48 4.1 量測環境設定 48 4.1.1 穩壓電路(Regulator) 48 4.1.2 濾波槽(Filter Tank) 49 4.2 量測結果 50 4.3 文獻比較 53 第五章 結論與未來展望 55 5.1 結論 55 5.2 未來展望 55 參考文獻 56

[1] W. J. Tompkins, “Biomedical Digital Signal Processing”, Prentice-Hall International, 1993.
[2] Youngcheol Chae, Minho Kwon, Gunhee Han , “A 0.8-uW switched-capacitor 88-dB audio sigma-delta modulator using a class-C inverter”, Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on. vol. 1, pp. 1152–5, May. 2004.
[3] Chauchin Su; Po-Chen Lin; Hungwen Lu ,” An Inverter Based 2-MHz 42-μW ΔΣ ADC with 20-KHz Bandwidth and 66dB Dynamic Range”, Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian. pp. 63-66, May. 2006.
[4] Youngcheol Chae; Gunhee Han,” Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator”, IEEE J.Solid-State Circuits,vol. 44, no. 2, pp. 458–472, Nov. 2009.
[5] Michel, F.; Steyaert, M.S.J. ,”A 250 mV 7.5 μW 61 dB SNDR SC ΔΣ Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS”, IEEE J.Solid-State Circuits,vol. 47, no. 3, pp. 709–721, Nov. 2012.
[6] L. Yao, M. S. J. Steyaert, and W. Sansen, “A 1-V 140-uW 88-dB audio sigma-delta modulator in 90-nm CMOS,” IEEE J.Solid-State Circuits,vol. 39, no. 11, pp. 1809–1818, Nov. 2004.
[7] Szu-Chieh Liu, and Kea-Tiong Tang, “A Low-voltage low-power sigma-delta modulator for bio-potential signals,” IEEE Life Science Systems and Applications Workshop,, pp. 24–27, Nov. 2011.
[8] 鄭子俞,「全差動三角積分調變器應用於生醫音頻前端電路」,國立交通大學電機工程學系碩士論文,中華民國九十七年十月。
[9] 林伯成,「應用於助聽器之低電壓低功率三角積分調變器」,國立交通大學
電機工程學系碩士論文,中華民國九十四年七月。
[10] Maghari, N., Sunwoo Kwon and Un-Ku Moon , “74dB SNDR Multi-Loop Sturdy-MASH Delta Sigma Modulator Using 35dB Open-Loop Opamp Gain”, IEEE J.Solid-State Circuits,vol. 47, no. 3, pp. 709–721, Nov. 2012.
[11] de la Rosa, J.M., Escalera, S., Perez-Verdu, B., Medeiro, F., Guerra, O., del Rio, R., Rodriguez-Vazquez, A. ,” A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta Modulator for low-power high-linearity automotive sensor ASICs”, IEEE J.Solid-State Circuits,vol. 44, no. 11, pp. 2246–2264, Nov. 2005.
[12] Szu-Chieh Liu and Kea-Tiong Tang, ”A Low-Voltage Low-Power Sigma Delta modulator for Bio-potential Signals”, IEEE LISSA, pp. 24–27, April. 2011.
[13] B. Razavi, Design of Analog CMOS Integrated Circuit.US, McGraw-Hill,2001.
[14] S. Rabii and B. A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators. Norwood, MA: Kluwer, 1999.
[15] P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti and A. Baschirotto, “Behavioral modeling of switched-capacitor sigma-delta modulators”, IEEE Trans.Circuits Syst. I, Fundam. Theory Appl., vol. 50, pp.352 - 364, Mar. 2003.
[16] David A. Johns, Ken Martin, “Analog Integrated Circuit Design”, John Wiley & Sons, Inc. 1997.

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