在三維積體電路的架構中，散熱問題強烈影響設計的可靠度。當晶片在運作的時候，晶片的三維結構導致高溫，並且阻礙散熱。
在本篇論文中，我們提出一個以面積、線長及功率密度為考量的叢集式三維積體電路佈局規劃，並且建構出精確的熱傳導模型來運算佈局規劃的溫度。經過溫度分布的分析計算後，散熱導孔將被放置在我們稱為熱導孔通道的預留區域內。熱導孔插入的運作程序將持續重複至最高峰溫度降至指定溫度。實驗結果顯示，我們所提出以精確的熱傳導模型來運算的實驗架構，可以有效率的降低熱點上的峰溫。

In 3D-IC architecture, thermal issues largely affect design reliability. The three-dimensional structure impedes heat dissipation and leads to high temperature when designs in execution. In this thesis, we propose a cluster-based 3D-floorplanning approach to place modules based on the factors of area, wire-length, and power density. Then we construct a precise thermal conduction model to compute temperature distribution in terms of the resultant floorplan. The thermal-vias will be placed at some reserved regions, called via-channels, by analytical computation based on temperature distribution. The thermal-via insertion procedure will repeat until the peak temperature is acceptable. The experiment results show that our framework is able to effectively reduce the peak temperature in hot-spots based on a precise temperature computation model.

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