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研究生： 李宏澤
Hung-Tse Lee
論文名稱： STT-RAM末級快取之低耗能設計
TSE: Two-Step Elimination for MLC STT-RAM Last-Level Cache
指導教授： 謝仁偉
Jen-Wei Hsieh
口試委員: 吳晉賢
Chin-Hsien Wu
劉一宇
Yi-Yu Liu
陳雅淑
Ya-Shu Chen
學位類別： 碩士
Master
系所名稱： 電資學院 - 資訊工程系
Department of Computer Science and Information Engineering
論文出版年： 2019
畢業學年度： 107
語文別： 英文
論文頁數： 43
中文關鍵詞： 旋轉力矩轉移隨機存取記憶體 、多層單元 、能量消耗 、兩部驟轉換 、末級快取
外文關鍵詞： STT-RAM, MLC, Energy consumption, Two-step transition, Last-level cache
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  •  上一筆

    • 1 Introduction 4 2 Background 7 2.1 Spin-Transfer Torque RAM (STT-RAM) . . . . . . . . . . . . 7 2.2 Multi-Level Cell (MLC) STT-RAM . . . . . . . . . . . . . . . 8 2.3 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Design of Two-Step Elimination (TSE) Scheme 13 3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Basic Idea of the TSE Scheme . . . . . . . . . . . . . . . . . . 14 3.3 Design of the TSE Tag . . . . . . . . . . . . . . . . . . . . . . 15 3.4 Tag Reversing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 Advanced Mode of the TSE Scheme . . . . . . . . . . . . . . . 19 3.6 Analysis of Space Overhead . . . . . . . . . . . . . . . . . . . 22 4 Performance Evaluation 29 4.1 Experiment Setup . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2 Pro le of Access Patterns . . . . . . . . . . . . . . . . . . . . 30 4.3 Statistic of Four Di erent Transition States . . . . . . . . . . 32 4.4 Comparison of Energy Consumptions . . . . . . . . . . . . . . 32 4.5 Comparison of Write Latencies . . . . . . . . . . . . . . . . . 33 5 Conclusion 37

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