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研究生： 邱春源
Chun-Yuan Chiou
論文名稱： 基於FPGA之GFP訊框搜尋最佳化的研究
A Study of GFP Frame Delineation Optimization Based on FPGA
指導教授： 王乃堅
Nai-Jian Wang
口試委員: 劉昌煥
Chang-Huan Liu
施慶隆
Ching-Long Shih
姚嘉瑜
Chia-Yu Yao
陳雅淑
Ya-Shu Chen
學位類別： 碩士
Master
系所名稱： 電資學院 - 電機工程系
Department of Electrical Engineering
論文出版年： 2008
畢業學年度： 96
語文別： 中文
論文頁數： 70
中文關鍵詞： 一般化訊框程序 、場效可程式邏輯閘陣列 、循環冗餘檢查碼-16
外文關鍵詞： GFP, FPGA, CRC-16
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  •  上一筆

    • 此篇研究提出了GFP (Generic Framing Procedure)訊框搜尋最佳化的方法，並且在FPGA (Field-Programmable Gate Array)上實現。利用FPGA可模組化的特性，使得硬體電路可共用且易於開發設計。所提出的方法除了可以簡化FPGA的邏輯閘 ，節省體積及成本外，也可以利用一個時脈週期同時處理64位元輸入的資料寬度做CRC-16的運算及比較，有別於傳統做法需多增加一個時脈週期的處理，因此可提高GFP訊框搜尋的效能。

    This thesis presents a new optimization approach for GFP (Generic Framing Procedure) frame delineation on an FPGA (Field-Programmable Gate Array). The using of FPGA characteristic of module enables the hardware circuit to share and easy to develop. Our approach not only can minimize logic gates of FPGA to save the volume and cost, but also performs 64-bit data size computation and comparison of CRC-16 on a single clock cycle. The proposed technique can improve the efficiency of the traditional methods that take more than one clock cycle to perform GFP frame delineation.

    摘要 I ABSTRACT II 誌謝 III 目錄 IV 圖索引 VI 表索引 VIII 第一章 緒論 1 1.1 研究背景與動機 1 1.2 研究目的與方法 4 1.3 論文組織 5 第二章 GFP介紹與訊框搜尋相關研究 6 2.1 GFP介紹 6 2.2 GFP訊框架構 8 2.2.1 Core Header 9 2.2.2 Payload Area 10 2.2.3 擾亂器與反擾亂器 12 2.3 GFP訊框識別演算法 13 2.4 相關研究與分析 16 第三章 循環冗餘檢查碼 17 3.1 CRC介紹 17 3.2 CRC原理分析 20 3.3 LFSR架構 22 3.4 LFSR和並行架構模擬比較 27 3.5 高速並行CRC運算演算法 29 3.6實驗結果與分析 33 3.7 CRC邏輯閘最佳化演算法 34 第四章 GFP訊框搜尋最佳化電路架構 42 4.1 FPGA硬體電路實現 42 4.1.1 六十四位元並行輸入電路 46 4.1.2 CRC-16運算電路 46 4.1.3 十六位元比較器電路及六十四位元輸出電路 47 4.2 模擬結果與比較 49 4.3 實驗結果與比較 51 4.3.1 實驗流程 51 4.3.2 量測工具及接線 53 4.3.3 模擬結果 53 4.3.4 實際量測結果 55 第五章 結論與未來展望 57 5.1 結論 57 5.2 未來展望 57 參考文獻 58 附錄 61 作者簡介 62

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