本論文提出二個不需要純量除法運算的近似 NLMS架構適應性濾波器來的設計與實現。本論文使用二進制簡化法與Canonical Signed-Digit (CSD) 簡化法來利用乘法運算來近似傳統的除法運算。在硬體優化方面，因為避免了除法的回授運算架構，可以大幅增加資料吞吐量，當與傳統除法架構相同吞吐量時，則能大幅降低面積及功耗。本論文使用FIR 架構實現近似 NLMS 演算法的適應性濾波器 VLSI 硬體，並進一步將其運用至硬體 IIR 適應性濾波器。
本論文所提出的近似NLMS架構適應性濾波器分別在基於Altera Cyclone IV EP4CE115F29C7N的DE2-115、TSMC 90 nm CMOS元件庫實現與驗證。在FIR架構下，FPGA部分的工作頻率可以達到91 MHz，二進制簡化法使用11773個邏輯元件和2555個暫存器，其功率消耗為271.67 mW， CSD簡化法使用11897個邏輯元件和2571個暫存器，其功率消耗為271.80 mW，與傳統除法架構同工作頻率下提升至236%的吞吐量。若以TSMC 90 nm CMOS元件庫合成，工作頻率可以達到270 MHz，並具有24.55 Msamples/sec.，消耗的邏輯閘數量分別為74 KGE與75KGE，功率消耗分別為11.99 mW與 12.30 mW，一樣提升了236%的吞吐量。

This thesis presents the design and implementation of two approximate NLMS architectures with adaptive filters that do not require division operations. This work uses binary simplification and canonical signed digit (CSD) simplification to replace the conventional division algorithm by using multiplication. When implemented in hardware, it can increase the throughput rate with the same clock frequency as the conventional division architecture, or reduce the clock rate and power consumption with a similar throughput rate as the conventional division architecture. In this work, we use the FIR architecture to implement the hardware for the approximate NLMS algorithm and further apply it to the adaptive IIR filter hardware.
The proposed approximate adaptive NLMS filters have been implemented and verified on the Altera Cyclone IV EP4CE115F29C7N-based DE2-115 FPGA board and in the TSMC 90 nm CMOS cell library. With the FIR architecture, the DE2-115 can operate at a clock rate of 91 MHz. The binary simplification uses 11773 logic components and 2555 registers, and the power consumption is 271.67mW. The CSD simplification uses 11897 logic components and 2571 registers, and the power consumption is 271.80 mW. The throughput rate can be increased to 236% at the same clock rate compared with the conventional NLMS-FIR architecture with 16-bit SRT division. Synthesized in TSMC 90nm CMOS cell library, the clock rate can reach 270MHz and the throughput rate can reach 24.55 Msamples/s. The gate count is 74 KGE and 75 KGE, and the power consumption is 11.99 mW and 12.30 mW, respectively.

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