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研究生: 周文祺
Wen-Chi Chou
論文名稱: 動態電壓應力對銅製程潛在缺陷之活化效能分析
The Latent Defect Activation Analysis of DVS in nanotech Cu Process
指導教授: 王秀仁
Show-Ran Wang
口試委員: 徐敬文
Ching-Wen Hsue
黃忠偉
Jong-Woei Whang
王秀仁
Show-Ran Wang
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2009
畢業學年度: 97
語文別: 中文
論文頁數: 83
中文關鍵詞: 動態電壓應力潛在缺陷奈米銅製程
外文關鍵詞: Dynamic voltage stress, latent defect, Cu process
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半導體積體電路的製造過程是歷經數百個製程步驟,而且涵蓋了物理、化學、熱力學、動力學、機械…等複雜領域交互配合而成。在製造過程中,難免會產生缺陷(defect),有些缺陷並不容易用傳統的測試方法發現,直到使用了一段時間後,這個缺陷才使電路的執行效率減低,進而發生故障。因此要如何提早發現而避免類似情況的發生就有許多方法被討論。
銅製程世代,加速壽命試驗下的失效模式是否具有代表性,關鍵是如何掌握適當的加速因子。面對元件尺寸不斷微縮,曾經是靜態的缺陷,現在己經變成延遲缺陷且不是百分之百能以傳統的測試流程完全偵測。將電壓與溫度作為加速因子並且以動態方式將適當應力加諸於積體電路部分電路中將會有助於缺陷的活化,並在分析電性測試資料在應力作用後的改變,可有效幫助我們及早偵測潛在缺陷可存在。
本篇論文首先介紹可靠度工程的相關理論基礎及定義,並簡單介紹如何進行加速夀命測試及數位積體電路測試法。接著深入探討半導體製程技術的演進,也會詳細說明傳統鋁製程和奈米銅製程之間的主要差異和新潛在缺陷產生的可能成因。了解造成失效模式的製程潛在缺陷後,可以藉由選擇適當的DVS應力條件與測試分析方法,對奈米銅製程缺陷活化與檢測有效度達到最佳化的調整。最後對本論文所討論議題做一總結,並提出未來可改善的方向。


Semiconductor technology which has hundreds of process steps during integrated chip manufacturing is a complicated field and it covers physics, chemistry, thermionics, dynamics and mechanics fundamentals. Defects would be generated during manufacturing and should be able to caught by traditional wafer sorting program, however, some latent defects would not be observed at early stage easily until chip is malfunction or degradation. Many approaches to detect and screen the latent defects have been discussing.
In the era of Cu process, optimization of the acceleration factor is the key to present the failure mode under accelerated life time test. Facing the continuously device dimension shrinkage, the defects are no more a static state, but will be easily to induce the timing delay which cannot be gated one hundred percent with traditional sorting procedure. To employ the voltage and temperature acceleration factor into the dynamic test sequence and datalog analysis will be helpful to activate latent defects and detect their existence in the following tests.
In the thesis, the reliability engineering principles, acceleration life time test and digital integrated chip testing methodologies will be initially introduced. The evolution of semiconductor industry and the benefit with Cu techniques of the deep submicron process will be illustrated as well. Then, to understand the major mechanisms of defects generation will be good to extract the optimized DVS condition for latent defect activation and detection. Conclusion will be summarized at last.

第一章 緒論 1.1 研究動機 1.2 論文架構 第二章 可靠度工程與晶圓測試介紹 2.1 可靠度工程起源 2.2 可靠度定義與基本介紹 2.2.1 可靠度的定義 2.2.2 失效率與浴缸曲線性 (Bathtub curve) 2.2.3 可靠度函數與韋伯分佈 (Weibull Distribution) 2.2.4 加速壽命實驗與Arrhenius Equation 2.3 奈米製程IC測試簡介 第三章 奈米世代製程技術簡介及挑戰 3.1 摩爾定律 (Moore’s Law) 3.2 半導體製程技術演進 3.3 銅製程連線技術與內連線介電層 3.3.1 銅金屬製程 3.3.2 雙鑲嵌銅製程連線技術 3.3.3 低介電係數材料在鑲嵌結構之運用 3.4新世代奈米製程技術挑戰 3.4.1 奈米製程常見缺陷 第四章 動態電壓應力測試對測試製程缺陷之有效性分析 4.1實驗方法與動態電壓加壓測試流程 4.2 動態電壓加壓和高溫燒烤對於缺陷活化的有效性分析 4.2.1 實驗數據統計 4.3 動態電壓加壓與對缺陷篩選能力分析 4.3.1 經DVS後在不同溫度下的測試環境之IDDQ資料分析 4.3.2經DVS後的測試環境之Speed資料分析 4.3.3經DVS後的測試環境之Vcc_min資料分析 4.4 動態電壓加壓測試與Burn-in測試能力分析 第五章 結論

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