本論文探討 DAC 在 SAR ADC 使用時會面臨洩漏和訊雜比(SNDR)/有效位元數(ENOB)的損失，為此使用一階電容交換技術與快速二元視窗切換技術來降低 DAC 電容以進一步節省功耗。由於電源電壓較低，SAR ADC 的取樣開關存在亞閾值洩漏，隨著取樣率越低，通過開關的洩漏電流會影響轉換精度，因為總”洩漏時間”會增加。此外 SAR ADC 必須保持儲存在電容器的電壓，直到位循環階段結束。本論文透過對靴帶式取樣開關做改善，以降低漏電流對 ADC 的影響。
本論文分為兩個晶片 :
類比至數位轉換器晶片以 TSMC 0.18μm CMOS 製程實現，整體晶片含I/O PADs 之晶片面積為 0.912mm2 。 其 中 類 比 至 數 位 轉 換 器 面 積 約 為0.25??2(627?? × 400??)。類比至數位轉換器解析度為十二位元，取樣頻率為1-KS/s，操作電壓為 0.5V。電路功耗為 8.264nW，訊號對雜訊與失真比(SINAD)為 69.69dB，有效位元(ENOB)為 11.28bits，無雜散動態範圍(SFDR)為 92.84dB，FOM 為 3.32fJ/c-s。
類比至數位轉換器搭參考電壓緩衝器之晶片以 TSMC 0.18μm CMOS 製程實現，整體晶片含 I/O PADs 之晶片面積為 0.991mm2。其中類比至數位轉換器與參考電壓緩衝器之面積約為 0.303??2(643?? × 472??)。類比至數位轉換器解析度為十二位元，取樣頻率為 1-KS/s，操作電壓為 0.5V；參考電壓緩衝器操作電壓為 0.7V。電路功耗為 3.175?W，其中類比至數位轉換器功耗為 8.264nW，參考電壓緩衝壓器則為 3.167?W，訊號對雜訊與失真比(SINAD)為 68.66dB，有效位元(ENOB)為 11.11bits，無雜散動態範圍(SFDR)為 87.11dB，FOM 為 3.74fJ/cs (無列入 Reference Buffer 功耗)。

This thesis investigates the challenges faced by DAC in SAR ADC, such as
leakage and loss of SNDR/ENOB. To further reduce power consumption, this thesis
uses a first-order capacitor switching technique and a fast binary window switching
technique to reduce DAC capacitance. As the power supply voltage decreases,
subthreshold leakage exists in the sampling switches of the SAR ADC. The leakage
current passing through the switches affects the conversion accuracy, as the total
"leakage time" increases when the sampling rate becomes lower. Additionally, the SAR
ADC must maintain the voltage stored in the capacitors until the bit cycle phase ends.
This thesis enhances the bootstrapped sampling switch to reduce the impact of leakage
current on the ADC.
There are two chips designed in as follows:
An analog-to-digital converter chip is implemented in a TSMC 0.18μm CMOS
process. The overall chip area, including I/O PADs, is 0.912mm2
. The analog-to-digital converter has an area of approximate 0.25mm2
(627μm × 400μm). The analog-to-digital
converter has a resolution of twelve bits, a sampling frequency of 1-KS/s, and an
operating voltage of 0.5V. The circuit consumes 8.264nW of power, with a signal-tonoise-and-distortion ratio (SINAD) of 69.69dB, effective number of bits (ENOB) of
11.28bits, spurious-free dynamic range (SFDR) of 92.84dB, and FOM of 3.32fJ/c-s.
Another analog-to-digital converter chip with a reference buffer is implemented in
TSMC 0.18μm CMOS process. The overall chip area, including I/O PADs, is 0.991mm2
.
The analog-to-digital converter and the reference buffer have an area of approximate
0.303mm2
(643μm × 472μm). The analog-to-digital converter has a resolution of twelve
bits, a sampling frequency of 1-KS/s, and an operating voltage of 0.5V. The reference
buffer has an operating voltage of 0.7V. The circuit power consumption is 3.175uW,
where the analog-to-digital converter consumes 8.264nW of power, and the reference
buffer power consumption is 3.167uW. The signal-to-noise-and-distortion ratio
(SINAD) is 68.66dB, the effective number of bits (ENOB) is 11.11bits, the spuriousfree dynamic range (SFDR) is 87.11dB, and the FOM is 3.74fJ/c-s (excluding the
reference buffer power).

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