在本論文中，一個頻寬為10 MHz的連續時間三角積分類比數位轉換器以TSMC 0.18 um 金氧半(CMOS)製程被設計，是應用於4G LTE的連續時間低通三角積分數位類比轉換器，其三角積分類比數位轉換器完成了晶片下線與量測結果;此晶片採用了CICFF迴路濾波器，相較於傳統CIFF架構，其電容式前饋方式電路是一種簡單的實現方式且具有低功率消耗特性，並且在量化器之後，加上一快速的回授路徑，增強雜訊轉移函數之階數(Noise Transfer Function,NTF)，有效的在頻寬內抑制雜訊，將其雜訊轉移至高頻，接著再使用數位濾波器濾除其雜訊
。此晶片時脈為320 MHz的情況下，在一個10 MHz的頻寬內這個調變器量測到59 dB的動態範圍，SNDR為58.95dB，IM3為-60 dB。在1.8 V的電源下量測的功率消耗是40.8 mW。包含Pads的晶片面積是1.056 (1.028 x 1.028) mm2。雖然三角積分數位類比轉換器能容忍類比電路的不完美特性，但其輸出需要經過抽取濾波器，此抽取濾波器由兩個串聯積分梳狀濾波器(CIC Filter)串聯組成.超取樣三角積分調變器輸出訊號經由抽取濾波器降頻為奈奎斯特數位類比轉換器，此抽取樣濾波器有效將高頻雜訊濾除掉，同時也防止高頻雜訊折疊到低頻頻帶內。

In this thesis, a 10 MHz CT ΣΔ modulators are designed and fabricated with TSMC 0.18um CMOS. The continuous time lowpass ΣΔ ADC for 4G LTE applications. The modulator is fabricated and taped out. In this chip, CICFF topology is applied. Compared with conventional CIFF topology, capacitive feedforward is a simple approach and has a merit of low power dissipation, and add a feedback path after quantizer to enhance the noise transfer function that effectively suppress noise in bandwidth and push noise to out-of-band and follow by a digital filter to filter the out of band of noise.
The ΣΔ analog-to-digital converter achieves a measured dynamic range of 59 dB over a 10 MHz signal bandwidth, SNDR of 58.95 dB, IM3 of -60 dB, power consumption of 40.8 mW at 1.8 V supply with 320 MHz clock frequency. Including pads, the overall chip area is 1.056 (1.028 x 1.028) mm2. Although ΣΔ analog-to-digital converter have high tolerance for the imperfection of analog circuit, a decimation filtering the output stream of ΣΔ modulators enhance the ADC’s performance. The decimation filter consists of two cascaded integrator and comb filter (CIC filter). The output signal of oversampling ΣΔmodulator is down converted by decimation filter; thus, a Nyquist rate bandwidth is obtained for the ΣΔ ADC. The decimation filter can filter noise from high frequency effectively and prevent high frequency noise from folding to desired baseband frequency range.

[1]M. Bolatkale, L. J. Breems, R. Rutten, and K. A. A. Makinwa, “A 4 GHz continuous-time ΔΣ ADC with 70 dB DR and -74 dBFS THD in 125 MHz BW,” IEEE J. Solid-State Circuits, vol. 46, pp. 2857-2868, Dec. 2011.
[2]H. Van de Vel, B. Buter, H. van der Ploeg, M. Vertregt, G. Geelen, and E. Paulus, “A 1.2-V 250-mW 14-b 100-MS/s digitally calibrated pipeline ADC in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1047–1056, Apr. 2009.
[3]S. Devarajan, L. Singer, D. Kelly, S. Decker, A. Kamath, and P. Wilkins, “A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS pipeline ADC,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3305–3313, Dec. 2009.
[4]A. Ali, A. Morgan, C. Dillon, G. Patterson, S. Puckett, P. Bhoraskar, H. Dinc, M. Hensley, R. Stop, S. Bardsley, D. Lattimore, J. Bray, C. Speir, and R. Sneed, “A 16-bit 250-MS/s IF sampling pipelined ADC with background calibration,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2602–2612, Dec. 2010.
[5]S. Louwsma, A. van Tuijl, M. Vertregt, and B. Nauta, “A 1.35 GS/s, 10 b, 175 mW time-interleaved AD converter in 0.13 μmm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 778–786, Apr. 2008.
[6]R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters, Piccataway, NJ: IEEE Press, 2005.
[7]H. Shibata, D. Paterson, S. R.. Schreier, N. Abaskharoun,e, I. Mehr, and Q. Luu, “A 375-mW quadrature bandpass Delta Sigma ADC with 8.5-MHz BW and 90-dB DR at 44 MHz,” IEEE J. Solid-State Circuits, vol. 41,no. 12, pp. 2632–2640, Nov. 2009.
[8]Z. Li and T. S. Fiez, "A 14-bit continuous-time delta-sigma A/D modulator with 2.5 MHz signal bandwidth," IEEE J. Solid-State Circuits, vol. 42, pp. 1873-1883, Sep. 2007.
[9]W. Yang, W. Schofield, H. Shibata, S. Korrapati, A. Shaikh, N. Abaskharoun, and D. Ribner, ”A 100mW 10 MHz-BW CT ΔΣ Modulator with 87dB DR and 91dBc IMD,” ISSCC Dig. Tech. Papers , 2008, pp. 498–499.
[10]L. Dorrer, F. Kuttner, P. Greco, P. Torta, and T. Hartig. “A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-μm CMOS,” IEEE J. Solid-State Circuits, vol. 40, pp. 2416-2427, Dec. 2005.
[11]R. Schreier, N. Abaskharoun, H. Shibata, D. Paterson, S. Rose, I. Mehr, and Q. Luu, “A 375-mW Quadrature Bandpass Delta Sigma ADC With 8.5-MHz BW and 90-dB DR at 44 MHz,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2632-2640, Dec. 2006.
[12]B. Javid, “Low-Power Delta-Sigma A/D Design for Broadband Applications,” Master Thesis, Toronto University, 2006.
[13]F. Medeiro, A. Perez-Verdu, and A. Rodriguez-Vazquez, Top-Down Design of High-Performance Sigma-Delta Modulators, Kluwer Academic Publishers, 1999.
[14]G. I. Bourdopoulos, A. Pnevmatikakis, V. Anastassopoulos, and T. L. Deliyannis, Delta-Sigma Modulators, Imperial College Press, 2009.
[15]M. Ortmanns and F. Gerfers, Continuous-Time Sigma-Delta A/D Conversion, New York: Springer, 2006.
[16]A. Marques, V. Peluso, M. S. Steyaert, and W. M. Sansen, “Optimal Parameters for ΔΣ Modulator Topologies,” IEEE Trans. Circuits Syst. II, vol. 45, No. 9, pp. 1232-1241, Sept. 1998.
[17]B. C. Nordick, “Dynamic element matching techniques for delta-sigma ADCs with large internal quantizers,” Master Thesis, Brigham Young University, 2004.
[18]Z. Li, “Design of a 14-bit continuous-time delta-sigma A/D modulator with 2.5MHz signal bandwidth,” Ph.D. Thesis, Oregon State University, 2006.
[19]Paulo G. R. Silva and Johan H. Huijsing, High-Resolution IF-to-Baseband Sigma-Delta ADC for Car Radios, Springer, 2008
[20]S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters-Theory, Design, and Simulation. Piccataway, NJ: IEEE Press, 1996.
[21]S. B. Kim, S. Joeres, R. Wunderlich, and S. Heinen, “A 2.7 mW, 90.3 dB DR continuous-time quadrature bandpass sigma-delta modulator for GSM/EDGE low-IF receiver in 0.25 μm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 891-900, Mar. 2009.
[22]A. Hart and S. P. Voinigescu, “A 1 GHz bandwidth low-pass ΣΔ ADC with 20-50 GHz adjustable sampling rate,” IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1401-1414, May 2009.
[23]L. Breems and J. H. Huijsing, Continuous Time Sigma Delta Modulation for A/d Conversion in Radio Receivers, Springer, 2001.
[24]F. Munoz, “A 4.7 mW 89.5 dB DR CT Complex DS ADC with Built-in LPF,” IEEE ISSCC Dig. Tech. Papers, pp. 500-501, Feb. 2005.
[25]M. S. Kappes, “A 2.2-mW CMOS Bandpass Continuous-Time Multi-bit ΔΣ ADC with 68 dB of Dynamic Range and 1-MHz Bandpass for Wireless Applications,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1098-2003, Jul. 2003.
[26]V. Peluso, A. Marquez, M. Steyaert, and W. Sansen, “Optimal Parameters for Single Loop ΣΔ modulator,” IEEE International Sym. on Circuit and Systems, pp. 57-60, June 1997.
[27]N. Yaghini, Design of a Wideband Quadrature Continuous-Time Delta-Sigma ADC, M.S thesis, University of Toronto, 2004.
[28]A. Van den Bosch, M. Borremans, S. J. Steyaert, and W. Sansen, “A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. 36, pp. 315-324, Mar. 2001.
[29]T. H. Kuo, K. D. Chen, and H. R. Yeng, “A wideband CMOS sigma-delta modulator with incremental data weighted averaging,” IEEE J. Solid-State Circuits, vol. 37, pp. 11-17, Jan. 2002.
[30]W. L. Yang, W. H. Hsieh ,and C. C. Hung, “A third-order continuous-time sigma-delta modulator for Bluetooth,” VLSI Design, Automaion and Test , pp.247-250, April 2009.
[31]S. B. Kim et al., “Continuous-time quadrature bandpass sigma-delta modulator for GPS/Galileo low-IF receiver,” in Proc. IEEE Int. Workshop on Radio-Frequency Integration Technology, Dec. 2007, pp. 127-130.
[32]A. Hart and S. P. Voinigescu, “A 1 GHz bandwidth low-pass ΔΣ ADC with 20-50 GHz adjustable sampling rate,” IEEE J. Solid-State Circuits, vol. 44, pp. 1401-1414, May 2009.
[33]C. Y. Lu, J. F. Siva-Rivas, P. Kode, J. Siva-Martinez, and S. Hoyos, “A sith-order 200 MHz IF bandpass sigma-delta modulator with over 68 dB SNDR in 10 MHz bandwidth ,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp.1122-1136, Jun. 2010.
[34]D. Johns and K. Martin, Analog Integrated Circuit, Wiley, 1997.
[35]R. R. Anantha, “A programmable CMOS decimator for sigma-delta analog-to-digital converter and charge pump circuits,” Master Thesis, Bachelor of Technology, Jawaharlal Nehru Technological University, India, May 2005.
[36]James Candy, “Decimation for Sigma-Delta Modulation,” IEEE Transaction on Communications, Vol. COM-34, pp. 72-26, Jan. 1986.
[37]Brian Brandt, Oversampled Analog-to-Digital Conversion, Ph.D. Dissertation, Stanford University, 1991.
[38]R. E. Crochiere and L. R. Rabiner, Multirate Digital Signal Processing, Prentice Hall,1983.
[39]B. P. Brandt and B. A. Wooley, “A Low-Power, Area-Efficient Digital Filter for Decimation and Interpolation,” IEEE J. Solid-State Circuits, vol. 29, no. 6, pp. 679-687, June. 1994.
[40]M. T. Heath , Scientific Computing: An Introductory Survey, McGraw-Hill, 2002.
[41]N. H. E. Weste and D. Harris, CMOS VLSI Design- A Circuits and Systems Perspective, 3rd edition, Addison Wisley, NY, 2005.
[42]L. Wanhammar and H. Johansson. Digital Filters. LiU-Tryck, 2007.
[43]L. Cederstrom, Power Efficient Digital Decimation Filters for ΣΔ ADCs, M.S thesis, Linkoping University, 2009.
[44]Y. M. Hasan, L. J. Karam, M. Falkinburg, A. Helwig, and M. Ronning, “Canonic signed digit FIR filter design,” in Asilomar Conference on Signals, Systems and Computers, pp. 1653-1656, Oct. 2000.
[45]Y. L. Guillou, O. Gaborieau, P. Gamand. M. Isberg, P. Jakobsson, L. Jonsson, D. L. Deaut, H. Marie, S. Mattisson, L. Monge, T. Olsson, S. Prouet, and T. Tired, “Highly Integrated Direct Conversion Receiver for GSM/GPRS/EDGE With On-Chip 84-dB Dynamic Range Continuous-Time ΣΔ ADC,” ,” IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 403-411, Dec. 2005.
[46]J. C. Morizio, M. Hoke, T. Kocak, C. Geddie, C. Huaghes, J. Perry, M. H. Hood, G. Lynch, H. Kondoh, T. Kumamoto, T. Okuda, H. Noda, T. Miki, and M. Nakaya, “14-bit 2.2- MS/s sigma-delta ADC’s,” IEEE J. Solid-State Circuits, vo35, no. 7, pp. 2857-2868, Jul. 2000.
[47]S. Gupta, D. Gangopadhyay, H. Lakdawala, J. C. Rudell, and D. J. Allstot, “A 0.8–2 GHz fully-integrated QPLL-timed direct-RF-sampling bandpass ΣΔ ADC in 0.13 um CMOS,” ,” IEEE J. Solid-State Circuits, vol. 47, no. 5, pp. 1141-1152, May. 2012.
[48]B. Pandita and K. W. Martin, “Oversampling A/D Converters With Reduced Sensitivity to DAC Nonlinearities,” IEEE Trans. Circuits Syst. II, vol. 56, no. 11,pp. 840–844, Dec. 2009.
[49]J. A. Cherry and W. M. Snelgrove, “Clock Jitter and Quantizer Metastability in Continuous-Time Delta–Sigma Modulators,” IEEE Trans. Circuits Syst. II, vol. 46, No. 9, pp. 661-676, June. 1999.
[50]L. J. Breems, R. Rutten, R.H. M. van Veldhoven, and G. van der Weide, “A 56 mW continuous-time quadrature cascaded delta sigma modulator With 77 dB DR in a Near Zero-IF 20 MHz Bandwidth,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2696-2705, Dec. 2007..
[51]R. Yu and Y. P. Xu, “Electromechanical-filter-based bandpass sigma-delta modulator,” IEEE Trans. Circuits Syst.Ⅱ, vol. 56, no. 7, pp. 550-554. Jul. 2009.
[52]A. Gupta, S. Ahmadi, and M. Zaghloul, “A 400 MHz delta-sigma modulator for bandpass IF digitization around 100 MHz with excess loop delay compensation,” in Proc. IEEE Int. Symp. Circuit and Systems, Rio de Janeiro, Brazil, May 2011, pp. 1375-1378.
[53]Song-Bok Kim, Stefan Joeres, Ralf Wunderlich, and Stefan Heinen, “A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25 um CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 891-900, Mar. 2009.
[54]Jinghua Zhang, Yong Lian, Libin Yao and Bo Shi, “A 0.6-V 82-dB 28.6-uW Continuous-Time Audio Delta-Sigma Modulator, “ IEEE J. Solid-State Circuits, vol. 46, no. 10, pp 2326-2335, Oct. 2011.
[55]Hajime Shibata, Richard Schreier, Wenhua Yang and Ali Shaikh, “A DC-to-1 GHz Tunable RF ∆∑ ADC Achieving DR = 74 dB and BW = 150 MHz at f0 = 450MHz Using 550mW, “ IEEE J. Solid-State Circuits, vol. 47, no. 12, pp 2888-2897, Dec. 2012.
[56]Vikas Singh, Nagendra Krishnapura, Shanthi Pavan and Baradwaj Vigraham, “ A 16 MHz BW 75 dB DR CT ∆∑ ADC Compensated for More Than One Cycle Excess Loop Delay, “ IEEE J. Solid-State Circuits, vol. 47, no. 8, pp 1887-1894, Aug. 2012.
[57]Ramin Zanbaghi, Pavan kumar Hanumolu and Terri s. Fiez, “ An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ∆∑ Modulator Dissipating 13.7-mW, “ IEEE J. Solid-State Circuits, vol. 48, no. 2, pp 487-501, Feb. 2013.