此文章分為三個部分，第一個是一個寬頻範圍鎖定除三/除五除頻器，第二個是寬頻範圍鎖定除五除頻器，最後一個是寬頻範圍鎖定除三除頻器，三者皆使用了標準台積電0.18微米製程去實現。
第一個電路，呈現一個電容叉對共振腔震盪器，實現寬頻注入鎖定除三/除五除頻器，此除頻器使用台積電矽鍺0.18微米製程，晶片面積為0.817 * 1.176 mm2。此電路包含一組雙注入訊號的N型金氧半電晶體並聯共振腔三個電感、兩個電阻、兩個電容所以及兩個N型金氧半電晶體交錯耦合對為中心所組成的電壓控制震盪器所組成。工作電壓操作在0.9伏，消耗功率為7.05mW，在注入強度為0 dBm時，除三的除頻範圍從5.8 GHz至 10 GHz，百分比為53.16%，除五的除頻範圍 從11.2GHz至14.2GHz，百分比為23.6%。
第二個電路描述一個超寬鎖頻範圍除五注入鎖定除頻器，是使用 TSMC 0.18 μm CMOS製程，晶片面積為0.982 × 1.128 mm2。此注入鎖定除頻器是使用雙諧振RLC共振腔以及線性混波器來擴大鎖頻範圍。量測結果為供應電壓1.15 伏特，功耗為9.04 mW。注入訊號為0 dBm時，其除五鎖頻範圍為11.3至15.75 GHz (32.9%)。
第三個電路研究偏壓對雙諧振除三注入鎖定除頻器的特性，0.18微米的互補式金氧半導體雙諧振重疊或非重疊的鎖定頻率範圍是依偏壓條件決定。量測結果為供應電壓0.8伏特功耗為9.57 mW，注入訊號為0 dBm時，其除三鎖頻範圍為7至11.7 GHz (50.26%)。

First, a wide locking range divide-by-3 and divide-by-5 injection-locked frequency divider (ILFD) using a standard 0.18μm BiCMOS process is presented. The ILFD circuit bases on capacitive cross-coupled oscillator and uses resonator with resistor to enhance the locking range. The power consumption of the ILFD core is 7.05mW. The divider’s free-running frequency is around 2.516GHz, and at the incident power of 0dBm the divide-by-5 locking range is 3 GHz (23.6%), from the incident frequency 11.2 to 14.2GHz; the divide-by-3 locking range is 4.2 GHz (53.16%), from the incident frequency 5.8 to 10GHz.
Secondly, a wide locking range divide-by-5 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process is presented. The ILFD circuit is realized with a cross-coupled n-core MOS dual-resonance RLC-tank oscillator with linear mixer to extend the locking range. The core power consumption of the ILFD core is 9.04 mW. The divider’s free-running frequency has dual-bands at 3.12 and 2.62 GHz by switching the varactor’s control bias, and at the incident power of 0 dBm the locking range is 4.45 GHz (32.9%), from the incident frequency 11.3 to 15.75 GHz.
Finally, this thesis studies the bias effect on the performance of a divide-by-3 injection-locked frequency divider (ILFD) with dual-resonance (DR) RLC resonator. The 0.18 μm CMOS DR ILFD circuit has overlapped and non-overlapped dual-band locking ranges depending upon the bias condition. The ILFD was fabricated in TSMC 0.18 μm CMOS technology and occupies a die area of 0.8379 ×0.935mm2.

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