複晶矽(polysilicon)薄膜電晶體(TFT)技術對主動式矩陣液晶顯示器而言是一種新興的關鍵技術，它提供了將主動矩陣及驅動電路整合在同一基板上的可能性。然而，傳統的自我對準型(self-aligned)的複晶矽薄膜電晶體的電特性上卻存在了幾個不欲發生的效應，包括大的關閉狀態(off-state)的電流(leakage current，漏電流)，紐結效應(kink effect)和熱載子引起電性操作上的不穩定性。 這些效應與存在於汲極端與通道間的高電場有很大的關聯。因此，必須降低汲極端的電場以改善上述的現象。在本篇論文中，將分析擁有大角度離子佈植汲極結構的新式複晶矽薄膜電晶體。
首先，製造三種擁有不同汲極結構的複晶矽薄膜電晶體，他們是：傳統型單一汲極/源極的薄膜電晶體、擁有輕摻雜汲極(Lightly-Doped-Drain, LDD)結構的薄膜電晶體以及擁有大角度離子佈植汲極(large-angle-tilt-implanted drain, LATID)結構的薄膜電晶體。接著，我們研究用不同的製程參數所形成的LDD TFTs的電特性，例如LDD離子佈植劑量及能量。由實驗的結果中，將可以確認不同LDD的製程參數與薄膜電晶體的電特性之間的關係。同樣地，我們也會討論藉由各種LATID佈植劑量、佈植能量及佈植角度所形成的薄膜電晶體的電特性。由實驗結果將發現離子佈植的劑量和能量影響LDD 和LATID薄膜電晶體的操作性能。而LATID離子佈植的角度對薄膜電晶體的操作性能更是有深刻的影響。
最後，我們比較傳統型單一汲極/源極的薄膜電晶體、擁有輕摻雜汲極(Lightly-Doped-Drain, LDD)結構的薄膜電晶體以及擁有大角度離子佈植汲極(large-angle-tilt-implanted drain, LATID)結構的薄膜電晶體的電特性。結果顯示擁有大角度離子佈植汲極(large-angle-tilt-implanted drain, LATID)結構的薄膜電晶體比起傳統型單一汲極/源極的薄膜電晶體、擁有輕摻雜汲極(Lightly-Doped-Drain, LDD)結構的薄膜電晶體將會擁有更低的漏電流。因為它對藉由陷阱狀態所產生的載子發射機制能更有效的抑制。而且，擁有大角度離子佈植汲極(large-angle-tilt-implanted drain, LATID)結構的薄膜電晶體其衝擊游離電流(與元件使用之可靠度相關)的峰值比起傳統型單一汲極/源極的薄膜電晶體、擁有輕摻雜汲極(Lightly-Doped-Drain, LDD)結構的薄膜電晶體也會小的多。因此，擁有大角度離子佈植汲極(large-angle-tilt-implanted drain, LATID)結構的薄膜電晶體將可以達到優越的元件特性以及可靠度。

Polycrystalline silicon (polysilicon) thin film transistor (TFT) technology is emerging as a key technology for active matrix liquid crystal displays, allowing the integration of both active matrix and driving circuitry on the same substrate. However, conventional self-aligned polysilicon TFTs present several undesired effects in the electrical characteristics, including large off-state currents (leakage), kink effect and hot carrier instabilities. These effects are related to the presence of high electric fields at the drain junction and electric field near the drain region relief is essential. In this thesis, a novel poly-Si TFTs formed by using the large-angle-tilt-implanted-drain (LATID) scheme has been analyzed.
First, three types TFTs with different drain structure were fabricated. They are the conventional single source/drain TFTs, the Lightly-Doped-Drain (LDD) TFTs and the large-angle-tilt-implanted drain (LATID) TFT. Next, the electrical characteristics of the LDD TFTs formed with different fabrication parameters such as LDD implantation doses and implanting energies were investigated. From the results, the relation between electrical characteristics of the LDD TFTs and such process parameters has been identified. In the same ways, electrical characteristics of the LATID TFTs were also studied. The LATID TFTs are formed with various LATID doses, various LATID energies and various LATID tilt angle. It is found that the implantation dose and implantation energy affected the performance of the LDD and the LATID TFTs. The implantation tilt angle of the LATID TFTs, moreover, has a most profound influence on the performance of the LATID TFTs.
Finally, the electrical characteristics of the conventional single source/drain TFTs, the LDD TFTs and the LATID TFTs were compared. It could be found that the LATID TFTs achieve much smaller leakage than both the conventional single source/drain TFTs and the LDD TFTs, attributable to the more effective suppression of carrier emission via trap states. Moreover, the peak impact ionization current, associated with the device reliability, of the LATID TFTs is also significantly smaller than that of the conventional TFTs and the LDD TFTs. As a result, a poly-Si TFTs with excellent device characteristics and reliability can be implemented by simply using the LATID fabrication scheme.

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