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Author: 黃之鴻
Chih-hung Huang
Thesis Title: 一個32位元多執行緒CPU架構研究與實現
The Design and Verification of a 32-bit Multithreading CPU Architecture
Advisor: 林銘波
Ming-bo Lin
Committee: 陳郁堂
Yie-tarng Chen
陳維美
Wei-mei Chen
Degree: 碩士
Master
Department: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
Thesis Publication Year: 2013
Graduation Academic Year: 101
Language: 中文
Pages: 65
Keywords (in Chinese): 中央處理單元 、ARM 、精簡指令集 、多執行緒
Keywords (in other languages): CPU, ARM, RISC, multithreading
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    • 在本篇論文中，我們設計並實現了一個與ARMv4T指令集架構相容的微處理器智財(Intellectual Property, IP) ─ HT-ARM9TM。為了改善~Proto3-ARM9TM~處理器效能，本論文選擇從多執行緒的議題著手，在承襲Proto3-ARM9TM的基本架構下，設計了配合處理器特性的執行緒管理單元：Thread-dispatcher，並配合多執行緒處理的特性，設計對應的記憶體存取路徑、暫存器存取路徑以及其他管線架構的修改。藉由適當的切換多執行緒的指令，使HT-ARM9TM處理器能有效的減少Proto3-ARM9TM處理器因危障產生的時間浪費。
    HT-ARM9TM微處理器智財已在Xilinx的Virtex-5 XC5VLX110-FF676 FPGA上實現，其整體系統使用了9397個LUT，32個Block RAM，其最高操作頻率(含AMBA匯流排系統)為31 MHz。其處理器核心與Proto3-ARM9TM處理器核心做比較，操作頻率由45.2 MHz提升至45.7 MHz，相同測試程式下的IPC由0.7提升至0.856，整體效能則增加23.64%。

    In this thesis, an ARMv4T instruction set architecture compatible microprocessor IP (Intellectual Property), HT-ARM9TM, is proposed. In order to improve the performance of the Proto3-ARM9TM processor, we focus on the subject of multithreading. To follow the architecture of the Proto3-ARM9TM processor, we designed a thread management unit: Thread-dispatcher, that matches with the processor property. To match with the multithreading property, we designed the memory access paths, register files access paths, and the modification of other pipeline architecture. By switching instructions of threads appropriately in the HT-ARM9TM processor, it can reduce the cycle wastes due to the hazards of the Proto3-ARM9TM processor.
    The HT-ARM9TM processor are implemented and verified at Xilinx Virtex-5 XC5VLX110-FF676 FPGA. The HT-ARM9TM processor consumes 9397 LUTs, 32 Block RAMs, and operates at maximum frequency (included the AMBA bus system) of 31 MHz. As compared with the HT-ARM9TM processor core and the Proto3-ARM9TM processor core, the maximum operating frequency is increased from 45.2 MHz to 45.7 MHz, the IPC is increased from 0.7 to 0.856, and the performance is increased by an amount of 23.64%.

    教授推薦書 論文口試委員審定書 中文摘要 英文摘要 目錄 表目錄 圖目錄 第一章 緒論 1.1 研究動機 1.2 章節編排 第二章 多執行緒處理的背景知識 2.1 執行緒的分割 2.2 執行緒的切換 2.3 執行時的時間浪費 2.4 多執行緒處理器的種類 2.5 現有的多執行緒處理器的特性 2.5.1 Intel處理器 2.5.2 Fuce處理器 2.5.3 MVP系統 第三章 ARM處理器的簡介 3.1 ARM處理器的發展 3.2 指令集架構 3.3 ARM處理器的運作模式 第四章 HT-ARM9TM處理器系統架構 4.1 ARM9TDMI的簡介 4.2 HT-ARM9TM的特性 4.2.1 Proto3-ARM9TM的特性 4.2.2 多執行緒處理 4.3 管線階級規劃 4.3.1 Proto3-ARM9TM處理器的管線階級 4.3.2 處理分支指令的效率分析 4.3.3 HT-ARM9TM處理器的管線階級 第五章 HT-ARM9TM的控制單元與資料路徑設計 5.1 控制單元與資料路徑的簡介 5.1.1 Thumb指令解碼器 5.1.2 指令控制器 5.1.3 乘加器 5.1.4 算術邏輯單元 5.2 Thread-dispatcher單元設計 5.2.1 執行緒的切換 5.2.2 優先權規劃 5.2.3 Thread-dispatcher ver.1 5.2.4 Thread-dispatcher ver.2 5.3 記憶體存取控制 5.4 暫存器檔案 第六章 HT-ARM9TM的危障處理 6.1 結構危障 6.2 資料危障 6.3 控制危障 第七章 FPGA驗證與結果分析 7.1 FPGA驗證流程 7.2 FPGA合成結果 7.3 效能評估 第八章 結論 參考文獻 授權書

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