隨著高速有線傳輸的發展，通道損耗的議題也逐漸受到重視，而等化器(Equalizer)正是解決訊號失真的可行方案。本論文使用前饋式等化器(Feed-Forward Equalizer, FFE)做為主要架構，並以常模演算法(Constant Modulus Algorithm, CMA)完成權重的收斂，然而過去文獻大多以PC或FPGA等方式實現權重收斂演算法的設計，此舉降低了電路運作的方便性，有鑑於此，本論文以全類比電路的方式將CMA實現於晶片內，由於其盲目等化器的架構，故本設計具有不需傳遞訓練序列，即可套用於接收端的良好適應性。

本論文提出一應用於5 Gb/s USB 3.0 傳輸線之基於常模演算法之前饋式等化器架構(CMA_FFE)，並以 TSMC 90 nm CMOS 製程實現，於1.2 V的工作電壓下，等化器電路的功率消耗為13.2 mW，晶片總面積為0.59 mm2，而核心部分面積為 0.058 mm2。在後模擬中，此等化器可補償USB 3.0 3 m 傳輸線在 Nyquist frequency 的16 dB損耗，模擬在30萬筆資料中，本論文之等化器可將 3 m 傳輸線之誤碼率從0.5降低為0，而實際電路量測上並無法將誤碼率改善，在本論文的最後會進行原因的分析。

In high-speed wireline communications, to reduce frequency-dependent channel loss is an important issue. The equalizer is an effective solution to resolve the frequency- dependent signal attenuation. This thesis proposed an on-chip constant-modulus-algorithm (CMA) -based Feed-Forward equalizer (FFE) to overcome this problem. Since CMA is a blind equalization method that does not need training sequence, the adaptive mechanism can be completely implemented on chip.
This thesis proposed the constant-modulus-algorithm-based Feed-Forward equalizer that compensates the cable loss for 5 Gb/s USB 3.0 application. The CMA-based FFE chip was realized in TSMC 90 nm CMOS process. The power consumption of equalizer is 14.4 mW under 1.2 V supply voltage. The total chip area is 0.59 mm2 with pads, and the core area is 0.058 mm2. In post layout simulations, the proposed equalizer has the ability to compensate the cable loss for USB 3.0. In this thesis, we assumed a 3-meter lines in simulations. The compensated cable loss are 16 dB for the 3 m cable at Nyquist frequency, respectively. After simulating a transmission of three hundred thousand bits, we show that the equalizer can improve BER from 0.5 to 0 for the 3-meter USB 3.0 cable. In fact, the equalizer can not improve the BER from 0.5 down to 0.

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