由於電子產品的功能日趨複雜，資料傳輸速率的不斷提高，DDR(Double Data Rate，雙倍資料速率)介面的設計需求越來越多，為解決設計過程中訊號品質和時序問題，以滿足多樣和複雜的應用需求，本研究從晶片、封裝到PCB (Print Circuit Board，印刷電路板)以共模擬的模擬設計方式著手，需透過不斷的優化，來提升高速記憶體介面設計的準確性。
本論文主要針對DDR3 SDRAM(Double Data Rate 3 Synchronous Dynamic Random Access Memory，雙倍資料速率同步動態隨機存取記憶體)的訊號完整性，對設計原理、開發流程、建立模型、模擬分析、優化方法等進行研究，重點對高速記憶體介面的特點、匹配方式、系統結構和ODT(On Die Termination)的影響等進行分析，並基於晶片→封裝設計→PCB設計，建立完整的模型，萃取接近真實工作情況的S參數模型，透過眼圖與時序分析，於ODT不開及開ODT 120Ω時的DDR3 DQ/DQS進行差異性比較，可明顯看出DQ0~DQ7的眼圖訊號在開啟ODT 120Ω後比不開ODT時，至少多開了30% 的眼寬及20% 的眼高，DQS的jitter小了200%，且DQ訊號皆無過衝的情況發生，可滿足DDR3之電氣特性規範。而在時序分析Tvb / Tva，開ODT 120Ω 的餘量比不開ODT時至少大10%，兩者同時皆可滿足DDR3規範之時序基準。

Due to the increasing complexity of electronic product features and constant improvement of data rate, DDR interface design has become more demanding. In order to solve the design process problem of signal quality and timing sequence, we must satisfy the needs of diverse and complex applications. This study is about researching from chip, package to Printed Circuit Board (PCB). With co-simulation analog design method and continuous optimization, we can improve the high speed memory interface design accuracy.
The research is mainly for DDR3 SDRAM of signal integrity to design principle, develop process, build model, simulation analyze and optimization method. It focuses on the impact analysis of the high speed memory interface features, impedance matched, system structure and On Die Termination (ODT). In addition, based on chip, package design, the PCB design, we build a complete model and trace close to the real work case of s parameter model. The performance of the eye diagram and timing sequence of the DDR3 DQ/DQS for ODT-off and ODT120Ω-open are compared. We can see ODT120Ω is better than ODT off at least 30% eye width and 20% eye height in DQ, smaller 200% jitter in DQS and no overshoot condition, that can pass JEDEC DDR3 electrical spec. The timing sequence analysis Tvb/Tva timing margin in ODT120Ω is better than ODT off at least 10% estimate, both can pass DDR3 timing spec.

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