本論文主要聚焦完整之佈局樣態產生方法，用以消弭任何數量元件之任何階次梯度誤差。所提之方法簡單易懂，完全補足歷年來佈局論文所提技術無法涵蓋所有佈局需求之缺憾。設計者可以藉由本論文所提出之方法，提前在電路設計階段藉由關鍵元件所需消弭之梯度階次預估每個元件所需之分割數量，實現電路與佈局統合設計，俾便進行更為精準之模擬，加速研發之進程。相關之作法不但經過MATLAB之行為模擬驗證，亦藉由晶片實作成功展現優於以往佈局方式之匹配效能。最後，更將所提之方法應用在儀測放大器關鍵元件之佈局上，以精巧之佈局取代複雜之電路設計，冀望達到可堪比擬之效能，證明所提佈局方法之神效。該儀測放大器以台積電0.18 mm標準 CMOS 製程實現，後模擬顯示增益誤差、頻寬與偏移電壓各為 2%、2.3MH與0.88 mV。共模與電源拒斥比分別是 58dB 與 106 dB。總晶片面積為0.129mm2 ，在 ±1.5V 電源供應下，消耗611mA電流。

This thesis provides the completion of layout technique utilizing devices placement in a special pattern to generate high-order of gradient error mismatch cancellation capability. The methodology presented in this thesis is an easily understandable mean of creating layout patterns in order to be used for any quantity and variety of devices, and any order of gradient error mismatch as required by the designer. Moreover, multiple layout patterns are available for layout engineers depending on the condition and size of the device. This proposed methodology has been rigorously tested through calculation and MATLAB simulation. The chip fabrication measurement has also shown successful results. Even though these chips are packaged by two different companies, all the measured chips continue to show that higher order pattern achieves better accuracy. An instrumentation amplifier design also has been made to implement the proposed methodology in order to achieve high order accuracy among the critical devices. It utilizes resistive feedback topology with balancing technique for its resistors. The design is implemented using TSMC 0.18 m standard process. Based on post-simulation, it has 2% gain error with 2.3MHz Bandwidth, 0.88mV offset voltage, 58dB CMRR and 106dB PSRR. The total chip area is 0.129mm2 with ±1.5V supply voltage 611A current consumption.

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