支援快速移動影片之高效能HEVC運動估計演算法與電路架構設計

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研究生：	曾昱豪 Yu-Hao Tseng
論文名稱：	支援快速移動影片之高效能HEVC運動估計演算法與電路架構設計 High-Throughput Motion Estimation Algorithm and VLSI Architecture for Fast Motion Sequences in HEVC Systems
指導教授：	沈中安 Chung-An Shen
口試委員:	阮聖彰 Shanq-Jang Ruan 林昌鴻 Chang-Hong Lin
學位類別：	碩士 Master
系所名稱：	電資學院 - 電子工程系 Department of Electronic and Computer Engineering
論文出版年：	2017
畢業學年度：	105
語文別：	中文
論文頁數：	33
中文關鍵詞：	高效率視訊編碼、運動估計系統、快速移動演算法、DSP48E
外文關鍵詞：	High Efficiency Video Coding, Motion estimation system, Fast motion algorithm, DSP48E
相關次數：	點閱：312 下載：5
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隨著科技的進步，數位影像已經成為了我們生活中的一部份，從智慧型手機到大型電子看板，隨處都可看見數位影像的蹤跡。不僅如此現代人為了追求更好的視覺享受，超高畫質(Ultra-High-Definition；UHD)影像(3840×2160)也逐漸成為現在硬體的必備規格中，然而為了支援這種高品質的影像處理在硬體上勢必會帶給系統運算單元以及記憶體空間巨大負擔，因此高效率影像壓縮系統的出現，藉由降低影像資料量有效的解決了硬體上運算、儲存、傳輸等相關問題。
本篇論文為了降低運動估計電路之硬體複雜度，對於演算法的進行了改良，並實現了ASIC和FPGA之硬體設計。在演算法方面為了減少運算複雜度，本篇論文參考了舊有的快速搜尋演算法並搭配可調式運動搜尋演算法進行改良，藉此大量降低所需搜尋的參考候選點，使在一個CTU下，其平均搜尋點為24個，與一般的快速演算法相比，可進一步降低54%的參考候選點數量，且平均壓縮品質只降低了1.57dB。另一方面，本篇論文也針對FPGA的合成結果進行優化，透過有效運用Xilinx Zynq UltraScale+系列之DSP48E特殊元件，使其和未優化的合成相比，能有效的減少25% LUT之數量。
本設計在ASIC方面使用台積電90奈米製程，在pre-layout的結果顯示，本設計共需要195.1K個邏輯閘數量，並以250MHz的工作頻率，以每秒60張的速度處理3840x2160的像素資料影片，而在FPGA設計上則使用Xilinx Zynq UltraScale+之平台，能以180MHz的工作頻率達成每秒30張3840x2160像素的資料影片。

This paper presents the algorithm and VLSI architecture of a high-throughput Motion Estimation (ME) for High Efficiency Video Coding (HEVC) systems. In order to reduce the ME computational complexity, this algorithm adopts the adaptive search range with fast search pattern that selects the most probable search directions and steps. The experimental results show that the average search candidates of the proposed algorithm can reduce 54% with only 1.57% dB rise in average BD-rate compared to the conventional fast-search example in fast motion sequence. To show the efficiency of the proposed algorithm, two architectures were designed and they were synthesized for ASIC based on TSMC 90nm technology and for FPGA Xilinx Zynq UltraScale+. Synthesis results show that the design can achieve 60 frames per second (fps) and 30 fps with resolution of 3840×2160 at the frequency of 250 MHz and 180 MHz in ASIC and FPGA. Moreover, for the purpose of optimizing the proposed architecture in FPGA, this work designed the process element with the optimal use of DSP48E blocks available on the Xilinx Zynq UltraScale+. The optimized result shows that can reduce 25% LUT utilization compare to the without optimization design.

摘要        II
Abstract        III
誌謝        IV
Contents        V
List of Figure    VII
List of Table    VIII
I. Introduction    1
II. Background and related works    4
2.1 HEVC Basic    4
2.2 Motion Estimation    5
a.    Motion Vector Prediction (MVP)    6
b.    Block Match Algorithm (BMA)    7
c.    Sum of Absolute Differences (SAD)    7
2.3 Related works    8
III. The Proposed Algorithm    10
3.1 The Overview of the proposed search algorithm    10
3.2 Proposed Adaptive Fast Search Algorithm (ASFA)    10
a.    First parts: The search range decision    10
b.    Second parts: Determine the search mode by PU modes    10
c.    Third parts: Fast pattern search (8 point search)    11
IV. Hardware Architecture Design    15
4.1 High Level Overview    15
4.2 Search range decision    15
4.3 Controller    16
4.4 Address generator    17
4.5 Cur. and Ref. Buffer    17
4.6 Processing Element    18
4.7 SAD combination tree    19
4.8 Cost comparator    19
4.9 MVD and SAD Buffer    19
V. Optimization based on FPGA platform    20
5.1 The Overview of optimization ni FPGA    20
5.2 Introduction for DSP48E    20
5.3 The Optimization design    21
VI. Experimental Result    22
6.1 PSNR Performance    22
6.2 Fast motion analyze    23
6.3 Computation complexity analyze    24
6.4 Timing analyze    25
6.5 Synthesis result    27
6.6 Comparison with Prior Arts    28
VII Conclusion    30
References    31

                                

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