研究生: |
王維庸 Wei-Yung Wang |
---|---|
論文名稱: |
CMOS類比/數位式脈波寬度控制迴路設計與實作 Design and Implementation of CMOS Analog/Digital Pulsewidth Control Loop |
指導教授: |
楊湰頡
Rong-Jyi Yang |
口試委員: |
姚嘉瑜
Chia-Yu Yao 張湘輝 Hsiang-Hui Chang 韓松融 Sung-Rung Han 莊基男 Chi-Nan Chuang 陳超群 Chao-Chyun Chen |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電機工程系 Department of Electrical Engineering |
論文出版年: | 2010 |
畢業學年度: | 98 |
語文別: | 中文 |
論文頁數: | 62 |
中文關鍵詞: | 脈波寬度控制迴路 、延遲鎖定迴路 、時脈產生器 、責任週期 |
外文關鍵詞: | pulsewidth control loop, delay locked loop, clock generator, duty cycle |
相關次數: | 點閱:231 下載:1 |
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隨著CMOS製程的進步,電路系統朝著高度整合與高速的方向發展,大部份的數位及混合訊號系統中,使用大量的時脈訊號來控制電路,因此,如何維持時脈訊號頻率、相位和責任週期的準確度,成為相當重要的課題。在頻率和相位的校正上,鎖相迴路與延遲鎖定迴路已經廣泛的被使用,而對於能夠調整責任週期的脈波寬度控制迴路,則是本論文討論的主題。
論文中首先對過去傳統式的延遲鎖定迴路與脈波寬度控制迴路進行介紹和分析,接著再把兩迴路當成主體,分別以類比和數位的方式,以0.18μm CMOS製程實作出兩種具有相位同步和責任週期調整能力的時脈產生器。
類比系統的部份,將過去被提出的單路脈波寬度控制迴路簡化為一階的系統,並維持與延遲鎖定迴路共同運作,達成目標功能。在迴路分析上,主要針對變形後的單路脈波寬度控制迴路建立模型,再以晶片實際量測的結果,來驗證模型的正確性。
最後,在一個全數位的系統上,利用特殊的運算選擇機制,將可變長度二位元搜索演算法延遲鎖定迴路,加入責任週期控制的功能,並修正系統中延遲線的架構來增加輸出時脈波寬的精確度,當然,系統中仍保留了相位同步、抗諧波鎖定和閉迴路的特性。
With the progress of the CMOS technologies. Circuit systems develop toward high speed and highly integrated. Most digital and mixed-signal circuits use a lot of clock signals to control a periodic notification at the requested time. Therefore, to keep the accuracies on frequency, phase and duty-cycle of clock signals is very important. For the issues on frequency and phase correction, phase locked loops (PLLs) and delay locked loops (DLLs) are widely used. Here we focus on the pulsewidth control loop (PWCL), which can adjust the duty cycle of the clock.
At first we will introduce the conventional delay-locked loop and pulsewidth control loop. By taking these two circuit system as the main body, two kinds of synchronous clock generator with adjustable duty cycles are implemented in the 0.18μm CMOS process.
In analog design, we simplified the single-path pulsewidth control loop to a first-order system and also working with a delay-locked loop to achieve the goal functions. For loop analysis, we built the mathematical model of the simplified single-path pulsewith control loop. Then we will verify the correctness of the model with experimental results.
Finally, we added a special operation circuit which provides the duty cycle adjustment function into all-digital variable successive approximation register delay-locked loop (VSAR DLL). In order to enhance the accuracy of the duty cycle of output clock, we modified the architecture of delay line in the system. Of course, the system properties of synchronous, harmonic-free and closed-loop operation are maintained.
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