在現在行動裝置的普及下以及越來越注重使用的效能和續航力，以至於電源管理晶片蓬勃的發展。在電源管理晶片中主要輸出電壓裝置為線性穩壓器與交換式穩壓器，而數位直流交換式轉換器則擁有較低的能量損耗以及可程式化等優點。電源管理晶片中所採取的動態電壓調變(Dynamic Voltage Scaling)技術，可使得整體系統達到最佳用電效能。但舊有的設計中通常是以一組直流轉換器來提供一組直流電壓值輸出，在搭配上其它外接線路來切換電壓，則會造成多餘的面積使用以及切換過程中的損耗。因此本論文提出了單端三段電壓輸出之數位直流轉換器來配合電源管理晶片改變不同狀態時所需求的供應電壓，減少了晶片中的線路數量，使得多餘的面積可提供開發者更多的使用空間。
本論文已經利用Xilinx Virtex 5 FPGA驗證單端三段電壓輸出交換式穩壓器的數位區塊，並且採用Full Custom流程設計出改良過的低功率類比/數位轉換器，在供應頻率25 MHz下可偵測1.32 V ~ 1.04 V之間的電壓並且功率消耗為0.45 μW。最後採用國家晶片中心的混合訊號晶片設計流程執行gate-level統整模擬，實現0.8 V、1.2 V和1.8 V三合一的降壓型數位直流轉換器的晶片。在不包含電感與電容下使用TSMC 0.18 μm元件庫製作成晶片面積為760 μm × 760 μm，供應頻率為25 MHz，工作頻率為3.125 MHz。

With the ubiquity of mobile devices and the increasing requirements of endurance and efficacy of these devices, power management chips have been popularized. The major component of a power management chip is a voltage regulator, which can be either a linear regulator or switching regulator. The benefits of switching regulators are their low power dissipation and the programmable feature. To maximize the power efficiency of the underlying system, the dynamic voltage scaling technique is widely used in power management chips. Hence, in this thesis, a variable-voltage switching regulator is proposed and implemented.
The proposed variable-voltage switching regulator has been implemented with Xilinx Virtex 5 FPGA accompanied with a low-power full-custom ADC (analog-to-digital converter). The output voltage ranges from 1.04 V to 1.32 V at the operating frequency of 25 MHz. The power dissipation is 0.45 W. In addition, the resulting chip is design with the TSMC 0.18-m process and simulated with the CIC mixed-signal flow at the gate level. The chip area is 760 m  760 m, excluding the inductor, capacitor, and power switching MOS transistors. The operating frequency is 25 MHz and the switching frequency is 3.125 MHz.

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