雙共振腔壓控振盪器與注入鎖定除頻器之研究｜國立臺灣科技大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	林哲逸 Che Yi Lin
論文名稱：	雙共振腔壓控振盪器與注入鎖定除頻器之研究 The Study of a Dual LC Tank Voltage-Controlled Oscillator and Injection-Locked Frequency Dividers
指導教授：	張勝良 Sheng-Lyang Jang
口試委員:	徐敬文 Ching-Wen Hsue 黃進芳 Jhin-Fang Huang 陳凰美 Hwan-Mei Chen
學位類別：	碩士 Master
系所名稱：	電資學院 - 電子工程系 Department of Electronic and Computer Engineering
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	110
中文關鍵詞：	壓控振盪器、注入鎖定除頻器
外文關鍵詞：	Voltage-Controlled Oscillator, Injection-Locked Frequency Dividers
相關次數：	點閱：829 下載：3
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

上一筆

此論文提出了一個壓控振盪器和二個注入鎖定除頻器，它們分別使用了標準台積電0.18微米和0.35微米CMOS製程去實現。
在壓控振盪器裡，此振盪器包含兩個由pmos為中心所組成的考畢子壓控振盪器單端VCO以串連形式堆疊而成，量測結果顯示其在其輸出之相位雜訊在頻率5.52 GHz其1 MHz處所量測之結果為-114.89 dBc/Hz，而其消耗功率在供應電壓1.6 V之下只有7.26 mW，其調變頻率則可從 5.15 GHz 到 5.85 GHz。
在注入鎖定除頻器(ILFDs)中，第一個注入鎖定除頻器是開關式電感雙頻帶注入鎖定除頻器，藉著開關電感的開關，可以達到雙頻帶除頻器。其鎖定範圍在低頻帶和高頻帶分別是從4.0 GHz 到 5.8 GHz 和從 8.48 GHz 到 9.3 GHz。第二個注入鎖定除頻器是互補式哈特萊注入鎖定除頻器，量測結果顯示其所鎖定範圍在注入功率0 dBm之下為14.94~16.05 GHz。

This thesis presents one voltage controlled oscillator and two injection locked frequency dividers, which are implemented by using standard TSMC 0.18um and 0.35um CMOS process respectively.
In voltage controlled oscillators, the oscillator contains two single ended VCO’s with two pMOS-core Colpitts oscillators stacked in series . The measurement shows the phase noise of -114.89 dBc/Hz at 1-MHz offset from the frequency 5.52 GHz while dissipating only 7.26 mW for the core VCO from the supply voltage of 1.6V. The tuning range of VCO is tunable from 5.15 GHz to 5.85 GHz.
In injection locked frequency dividers (ILFDs), the first injection locked frequency divider is a switched-inductor dual-band ILFD. By switching on/off the inductor switch, a dual-band frequency divider can be obtained. The locking ranges of low-frequency and high-frequency band are respectively from 4.0 GHz to 5.8 GHz and from 8.48 GHz to 9.3 GHz. The second injection locked frequency divider is a complementary Hartley ILFD. The measurement shows the locking range is from 14.94~16.05 GHz when the injection input power is 0 dBm.

中文摘要.......................................................I
ABSTRACT.......................................................II
誌謝...........................................................III
LIST OF FIGURES................................................VI
LIST OF TABLES.................................................VIII
CHAPTER 1 INTRODUCTION.........................................1
1BACKGROUND..................................................1
2THESIS ORGANIZATION.........................................3
CHAPTER 2 THE PRINCIPLE OF OSCILLATORS.........................4
1 BASIC THEORY OF OSCILLATORS................................4
1.1 Two-Port (Feedback) View.................................4
1.2 One-Port (Negative Resistance) View......................6
2 QUALITY FACTOR	.............................................8
3 PHASE NOISE................................................11
3.1 Defination of The Phase Noise............................11
3.2 Power and FOM............................................16
4 ON CHIP VARACTORS..........................................16
4.1 Diode Varactor...........................................17
4.2 MOS Varactor	.............................................18
5 ON CHIP INDUCTORS..........................................22
5.1 Spiral Inductor..........................................23
5.2 The Transformer..........................................28
6 THE POPULAR RESONATOR......................................33
6.1 Single Transistor Oscillator.............................34
6.2 Cross-Coupled Oscillator.................................37
6.3 Complementary Cross-Coupled Topology.....................38
7 PARAMETERS OF VCO’S.......................................41
CHAPTER 3  A DUAL LC TANKS CMOS VCO............................46
1 INTRODUCTION...............................................46
2 CIRCUIT DESIGN	.............................................47
3 MEASUREMENT RESULTS........................................52
4 CONCLUSION.................................................55
CHAPTER 4  A 0.35UM CMOS SWITCHED-INDUCTOR DUAL-BAND LC-TANK
           FREQUENCY DIVIDER...................................56
1 INTRODUCTION...............................................56
2 OVERVIEW OF FREQUENCY DIVIDER..............................57
2.1 Locking Range............................................58
2.1 Conventional LC-Tank Oscillator ILFD.....................60
2.2 Proposed Switched-Inductor Dual-Band LC-Tank Frequency
      Divider Design...........................................62
3 MEASUREMENT RESULTS........................................66
4 CONCLUSION.................................................74
CHAPTER 5  A COMPLEMENTARY HARTLEY INJECTION-LOCKED FREQUENCY
           DIVIDER	.............................................75
1 INTRODUCTION...............................................75
2 TAPPED INDUCTOR DESIGN.....................................76
3 CIRCUIT DESIGN OF COMPLEMENTARY HARTLEY VCO................77
4 CIRCUIT DESIGN OF COMPLEMENTARY HARTLEY ILFD...............82
5 MEASUREMENT RESULTS........................................84
6 CONCLUSION.................................................90
CHAPTER 6 CONCLUSIONS..........................................91
REFERENCES.....................................................93

                                

[1]J. Roggers, C. Plett, Radio frequency integrated circuit design, Artech House, 2003
[2]B. Razavi, RF microelectronics, Prentice Hall PTR, 1998.
[3]B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE J. Solid-State Circuits, vol. 31, pp. 331-343, 1996
[4]D. Leeson, “A simple model of feedback oscillator noise spectrum,” Proceedings of the IEEE, vol. 54, pp. 329-330, Feb. 1966.
[5]A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998.
[6]T. Lee and A. Hajimiri, “Oscillator phase noise: a tutorial,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 326-336, Mar. 2000.
[7]A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 717-724, May 1999.
[8]J. N. Burghartz, “Integrated RF and microwave components in BiCMOS technology,” IEEE Trans. Electron Devices, vol. 43, no. 9, pp. 1559-1570, 1996.
[9]Svelto, F. Erratico, P. Manzini, S. Castello, R. Dipt. di Ingegneria, Univ. di Bergamo, Dalmine, “A metal-oxide-semiconductor varactor,” IEEE Electron Device Lett., vol. 20, no. 4, pp. 164-166, 1999.
[10]P. Andreani, S. Mattisson, “On the use of MOS varactors in RF VCO’s,” IEEE J. Solid-State Circuits, vol. 35, pp. 905-910, 2000.
[11]R. L. Bunch, S. Raman, “Large signal analysis of MOS varactors in CMOS -Gm LC VCOs,” IEEE J. Solid-State Circuits, vol. 38, pp. 1325-1332, 2003
[12]J. Aguilera, and R. Berenguer, “Design and test of integrated inductors for RF applications”, Kluwer Academic Publishers, 2004.
[13]J. Craninckx, and M. S. J. Steyaert, “A fully integrated CMOS DCS-1800 frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2054-2065, 1998..
[14]Y. K. Koutsoyannopoulos, and Y. Papananos, “Systematic analysis and modeling of integrated inductors and transformers in RF IC design,” IEEE Trans. Circuits and System-II, vol. 47, no. 8, pp. 699-713, 2000.
[15]A . Zolfaghari, A. Chan, and B. Razavi, “Stacked inductors and transformers in CMOS technology,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 620-628, 2001.
[16]Y. Koutsoyannopoulos, “Novel Si integrated inductor and transformer structure for RF IC design,” Proc. ISCAS ‘99, vol. 2, pp. 573.576, 1999.
[17]C. Tang, C. Wu, and S. Liu, “Miniature 3-D inductors in standard CMOS process,” IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 471-480, 2002
[18]H. M. Greenhouse, “Design of planar rectangular microelectronic inductors,” IEEE Trans. on Parts, Hybrids and Packaging, vol. PHP-10, no.2, pp. 101-109, 1974.
[19]J. R. Long, “Monolithic transformers for silicon RF IC design," IEEE J. Solid-State Circuits, vol. 35, pp. 1368-1382, 2000.
[20]A. Zolfaghari, A. Chan, and B. Razavi, “Stacked inductors and transformers in CMOS technology," IEEE J. Solid-State Circuits, vol. 36, pp. 620-628, 2001.
[21]A. Hajimiri, and T. H. Lee, The design of low noise oscillators, Kluwer Academic Publishers, 1999.
[22]B. De Muer, M. Borremans, M. Steyaert, and G. Li Puma, “A 2-GHz low-phase-noise integrated LC-VCO set with flicker-noise upconversion minimization,” IEEE J. Solid-State Circuits, vol. 35, pp. 1034-1038, 2000..
[23]S . Levantino, C. Samori, A. Bonfanti, S.L.J. Gierkink, A.L. Lacaita, and V. Boccuzzi, “Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion,” IEEE J. Solid-State Circuits, vol. 37, pp. 1003.1011, 2002.
[24]A. Hajimiri and T. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 717–724, May 1999
[25]R. Aparicio and A. Hajimiri, “A noise-shifting differential Colpitts VCO,” IEEE J. Solid-State Circuits, vol. 12, no. 12, pp. 1728–1736, Dec. 2002.
[26]C. Y. Cha and S. G. Lee “A complementary Colpitts oscillator in CMOS technology,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 3, pp. 881 - 887, Mar. 2005
[27]S. H. Lee, Y. H. Chuang, S. L. Jang and C. C. Chen, ” Low-phase noise Hartley differential CMOS voltage controlled oscillator,” IEEE Microw. Wireless Compon. Lett., pp. 145-147, Feb. 2007.
[28]J. A. Hou, C. P. Chang, J. G. Su, C. W. Chen, T. S. Liou, S. C. Wang , and Y. H. Wang, ” A low supply voltage VCO Implemented by a single common-source 90nm CMOS transistor,” IEEE Microw. Wireless Compon. Lett., pp. 64-66, Jan. 2007.
[29]G. De Astis, D. Cordeau, J. M. Paillot, and L. Dascalescu, “A 5-GHz fully integrated full PMOS low-phase-noise LC VCO,” IEEE Solid-State Circuits, vol. 40, no. 10, pp. 2087–2091, Oct. 2005.
[30]Y. K. Chu and H.-R. Chuang, “A fully integrated 5.8 GHz U-NII band 0.18-um CMOS VCO,” IEEE Microw. Wireless Compon. Lett., vol. 13,no. 7, pp. 287–289, Jul. 2003.
[31]Y. H. Chuang, S.-H. Lee, R. H. Yen, S. L. Jang, J. F. Lee, and M. H. Juang, “A wide locking range and low voltage CMOS direct injection-locked frequency divider,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 5, pp. 299–301, May 2006..
[32]A. Kral, and A. A. Abidi, “RF-CMOS oscillators with switched tuning,” in Proc. IEEE CICC, May 1998, pp. 555–558.
[33]S. M. Yim and K. K. O, “Demonstration of a switched resonator concept in a dual-band monolithic CMOS LC-tuned VCO,” in Proc. IEEE CICC, May 2001, pp. 205–208.
[34]M. Tiebout, “A CMOS fully integrated 1 GHz and 2 GHz dual band VCO with a voltage controlled inductor,” ESSCIRC, pp.799 – 802, 2002.
[35]Z. Li and K. K. O, “A low-phase-noise and low-power multiband CMOS voltage-controlled oscillator,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1296 - 1302, 2005.
[36]M. A. Do, R. Y. Zhao, K. S. Yeo and J. G. Ma, “New wideband/ dualband CMOS LC voltage controlled oscillator. “ IEEE Proc. Circuits, Devices and Systems, Vol. 150 , pp. 453-459 Oct. 2003.
[37]V. Araiia, A. Suhrez, and P. Dorta, ”Dual-band frequency divider based on oscillation control,” 2004 IEEE MTT-S Digest.
[38]J. Craninckx and M. Steyaert, “A 1.75 GHz/3 V dual-modulus divide-by-128/129 prescaler in 0.7um CMOS,” in Proc. ESSCIRC, Sept.1995, pp. 254–257.
[39]D. Pfaff and Q. Huang, “A quarter-micron CMOS 1 GHz -VCO/prescaler-set for very low power applications,” in IEEE Custom Integrated Circuits Conf. Dig. Tech. Papers, May 1999, pp.649–652.
[40]Q. Huang and R. Rogenmoser, “Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks,” IEEE J. Solid-State Circuits, vol. 31, pp. 456–463, Mar. 1996
[41]J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18 um CMOS technology,” in Symp. VLSI Circuits Dig. Tech. Papers, June 2003, pp.259–262.
[42]H. D.Wohlmuth and D. Kehrer, “A high sensitivity static 2:1 frequency divider up to 27 GHz in 120 nm CMOS,” in Proc. Eur. Solid-State Circuits Conf., Firenze, Italy, Sept. 2002, pp. 823–826.
[43]M. Tiebout, “A 480 uW 2 GHz ultra low power dual-modulus prescaler in um standard CMOS,” in Proc. IEEE Int. Symp. Circuits and Systems,vol. 5, Geneva, Switzerland, May 2000, pp. 741–744.
[44]H. Wu, “Signal generation and processing in high-frequency/high-speed silicon- based integrated circuits,” PhD thesis, California Institute of Technology, 2003.
[45]R. Adler, “A study of locking phenomena in oscillators,” Proc. IEEE, vol. 61, pp.1380-1385, Oct. 1973
[46]H. Wu, and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 μm CMOS frequency divider with shunt-peaking locking-range enhancement,” ISSCC Digest of Tech. Papers. pp. 412-413, February 2001..
[47]M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE Journal of Solid-State Circuits, vol. 39, pp. 1170-1174, July 2004.
[48]H. R. Rategh, H. Samavati, and T. H. Lee, “A 5 GHz, 1 mW CMOS voltage controlled differential injection locked frequency divider,” Custom Integrated Circuits Conference, pp. 517-520 May 1999.
[49]K. Yamamoto, T. Norimatsu, and M. Fujishima, “High-speed and wide-tuning-range LC frequency dividers,” IEEE ISCAS 2004, pp. 361-364.
[50]G. De Astis, D. Cordeau, J. M. Paillot, and L. Dascalescu, “A 5-GHz fully integrated full PMOS low-phase-noise LC VCO,” IEEE J. Solid-State Circuits, vol. 40, no. 10, pp.2087-2091, Oct. 2005.
[51]A. Jerng, and C. G. Sodini, “The impact of device type and sizing on phase noise mechanisms,” IEEE J. Solid-State Circuits, vol. 40, pp. 360–369, 2005.
[52]P. W. Lai, L. Dobos, S. Long, "A 2.4GHz SiGe low phase-noise VCO using on chip tapped inductor," IEEE, ESSIRC, pp. 505-508, 2003.

簡易檢索 / 詳目顯示

相關論文