本論文係有關單回合連通物件標示演算處理器之軟/硬體整合設計與驗證，相關研究工作包含下列四大部分。
第一部分為連通物件標示演算法之軟體設計，在考量運算結果之特性及嵌入式系統之硬體資源限制後，發展出單回合連通物件標示演算法。
第二部分為設計與實現單回合連通物件標示演算處理器，利用雙倍資料傳輸率同步動態隨機存取記憶體儲存完整的二值化輸入影像以及影像處理後的編號物件框架座標資訊。演算處理器主要包含表初始化、物件編號、連通物件編號合併、連通物件資訊提取等諸副處理器，最後把以上設計的硬體整合並以Altera FPGA實現之。
第三部分為撰寫演算處理器之相關驅動程式以構成一個驗證系統，並透過遠端程序呼叫的方式控制此驗證系統來驗證其功能。
第四部分為演算處理器之整體軟/硬體之驗證與效能評估。
整體而言，本論文係以研究單回合連通物件標示演算法與設計其演算處理器為目標，並以Altera FPGA開發板實現之。透過不同的影像測試，證實本論文所發展之演算處理器有極佳的效能，其相關之軟硬體整合設計方法，亦可改善演算處理器設計與驗證流程的效率。

This thesis is relevant to the hardware/software co-design and verification of an algorithmic processor for single-pass-based connected component labeling. The research work consists of the following four parts.
The first part of the thesis focuses on the software design for the connected component labeling algorithms. After analyzing the characteristics of the computing results and considering the limitation of physical resources in the embedded systems, single-pass-based connected component labeling algorithms have been developed.
The second part of the thesis focuses on the hardware design for single-pass-based connected component labeling algorithms. A DDR SDRAM is used to store the whole binary input image and the coordinate information of the bounding box of the labeled components. The algorithmic processor comprises four sub-processors: table initializer, labeler, connected component combinator, and connected component information retriever. And, finally, these hardware designs are integrated together and implemented on an Altera FPGA development board.
The third part of the thesis focuses on writing the relevant drivers to construct a verification system for the algorithmic processor. Through using the remote procedure calls this system is controlled to verify the functionality of the processor.
The fourth part of the thesis focuses on the verification and performance evaluation of the whole hardware and software for the algorithmic processor.
Generally speaking, the goal of this thesis is to do the research on the single-pass-based connected component labeling algorithms and algorithmic processors for them are designed and implemented with the Altera FPGA development board. After verifying the algorithmic processors with various types of digital images, it has been shown that the algorithmic processors developed in this thesis have fabulous computing performance. Meanwhile, this approach of hardware/software co-design can also improve the efficiency of both design and verification flows for algorithmic processors.

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